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path: root/drivers/gpu/drm/nouveau/nvkm/engine
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2020-01-15drm/nouveau/gr/gf100-: use nvkm_blob structure for fecs/gpccs fwBen Skeggs3-33/+20
It serves the exact same purpose. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/pmu/gp10b: split from gm20b implementationBen Skeggs1-1/+1
ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GM20B/GP10B FWs have interface differences. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/acr: add stub implementation for all GPUs currently supported by ↵Ben Skeggs1-0/+12
SECBOOT PMU, SEC2 and GR will be modified to register their falcons with ACR before the main commit switching everything over. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/core: define ACR subdevBen Skeggs2-0/+3
This will replace the current SECBOOT subdev for handling firmware on secure falcons. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/disp/dp: fix typo when determining failsafe link configurationBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/gr/gv100-: modify gr init to match newer version of RMBen Skeggs4-16/+27
Will be used as a basis for implementing changes needed for Turing. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/gr/gk20a,gm200-: add terminators to method lists read from fwBen Skeggs1-10/+11
Method init is typically ordered by class in the FW image as ThreeD, TwoD, Compute. Due to a bug in parsing the FW into our internal format, we've been accidentally sending Twod + Compute methods to the ThreeD class, as well as Compute methods to the TwoD class - oops. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/gr/gf100-: remove dtorBen Skeggs2-3/+0
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/ce/gp10b: Use correct copy engineThierry Reding1-1/+1
gp10b uses the new engine enumeration mechanism introduced in the Pascal architecture. As a result, the copy engine, which used to be at index 2 for prior Tegra GPU instantiations, has now moved to index 0. Fix up the index and also use the gp100 variant of the copy engine class because on gp10b the PASCAL_DMA_COPY_B class is not supported. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/ltc/gp10b: Add custom L2 cache implementationThierry Reding1-1/+1
There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/tegra: Set clock rate if not setThierry Reding1-0/+12
If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/tegra: Avoid pulsing reset twiceThierry Reding1-6/+6
When the GPU powergate is controlled by a generic power domain provider, the reset will automatically be asserted and deasserted as part of the power-ungating procedure. On some Jetson TX2 boards, doing an additional assert and deassert of the GPU outside of the power-ungate procedure can cause the GPU to go into a bad state where the memory interface can no longer access system memory. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/fault: Add support for GP10BThierry Reding1-1/+1
There is no BAR2 on GP10B and there is no need to map through BAR2 because all memory is shared between the GPU and the CPU. Add a custom implementation of the fault sub-device that uses nvkm_memory_addr() instead of nvkm_memory_bar2() to return the address of a pinned fault buffer. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/gr/gk208-gm10x: regenerate built-in firmwareBen Skeggs2-786/+786
Commit 5fde30a2684041f9820aa9dc4fbd0009a45076a9 in envytools modified some of the Falcon V5 encodings, regenerate the relevant FW with this. Also modify build rules to include SPDX header in generated files. Tested on GM107, with no issues noted. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-08-23drm/nouveau/fifo/gk104-: fix parsing of mmu fault dataBen Skeggs10-26/+67
Pascal was particularly incorrect, as the register changed to be more in the same format as the MMU fault buffers are. Shouldn't have impacted much more than confusing MMU fault log messages. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-08-23drm/nouveau/fifo/gf1xx: convert to using nvkm_fault_dataBen Skeggs3-86/+106
Would like to be able to reuse gf100_fifo_intr_fault() for (some of) the later chipsets too, as it's identical. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau: fix bogus GPL-2 license headerBen Skeggs22-22/+22
The bulk SPDX addition made all these files into GPL-2.0 licensed files. However the remainder of the project is MIT-licensed, these files were simply missing the boiler plate and got caught up in the global update. Fixes: 96ac6d4351004 (treewide: Add SPDX license identifier - Kbuild) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau: fix bogus GPL-2 license headerIlia Mirkin72-72/+72
The bulk SPDX addition made all these files into GPL-2.0 licensed files. However the remainder of the project is MIT-licensed, these files (primarily header files) were simply missing the boiler plate and got caught up in the global update. Fixes: b24413180f5 (License cleanup: add SPDX GPL-2.0 license identifier to files with no license) Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Emil Velikov <emil.l.velikov@gmail.com> Acked-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau/disp/tu102-: wire up scdc parameter setterBen Skeggs1-0/+1
Regs seem valid here still, and tested on TU116. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau/core: recognise TU116 chipsetBen Skeggs1-0/+36
Modesetting only, still waiting on ACR/GR firmware from NVIDIA for Turing graphics/compute bring-up. Each subsystem was compared with traces, along with various tests to check that things generally work as they should, and appears compatible enough with the current TU117 code to enable support. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19drm/nouveau/mcp89/mmu: Use mcp77_mmu_new instead of g84_mmu_new on MCP89.Timo Wiren1-1/+1
Fix a crash or broken depth testing in all OpenGL applications that use the depth buffer on MCP89 (GeForce 320M) seen on a MacBook Pro Late 2010. The bug is tracked in https://bugs.freedesktop.org/show_bug.cgi?id=108500 Signed-off-by: Timo Wiren <timo.wiren@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-06-07Merge branch 'linux-5.2' of git://github.com/skeggsb/linux into drm-fixesDave Airlie1-3/+1
" This is a bit more than I'd like to be pushing at this point in a cycle, but it's a fairly important issue. There's been numerous reports of more recent GP10[2467] boards failing to load, and I've worked with NVIDIA FW engineers and tracked this down to the FW we've been using not properly supporting the boards in question. I've pushed an update to linux-firmware with the new FW version, which unfortunately contains API changes vs the older firmware. This series teaches the ACR subsystem inside nouveau enough to be able to deal with supporting multiple incompatible FW revisions, and adds support to the relevant chipsets for loading the newer FW revision, if it's available." Signed-off-by: Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv7pG+vur0Kn_TyU3ainnkvJVw07upnnaQNOToF+kzQtDQ@mail.gmail.com
2019-06-07drm/nouveau/core: pass subdev into nvkm_firmware_get, rather than deviceBen Skeggs1-3/+1
It'd be nice to have FW loading debug messages to appear for the relevant subsystem, when enabled. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-05-30treewide: Add SPDX license identifier - KbuildGreg Kroah-Hartman22-0/+22
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0 Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-16Merge tag 'drm-next-2019-05-16' of git://anongit.freedesktop.org/drm/drmLinus Torvalds2-4/+67
Pull drm fixes from Dave Airlie: "A bunch of fixes for the merge window closure, doesn't seem to be anything too major or serious in there. It does add TU117 turing modesetting to nouveau but it's just an enable for preexisting code. amdgpu: - gpu reset at load crash fix - ATPX hotplug fix for when dGPU is off - SR-IOV fixes radeon: - r5xx pll fixes i915: - GVT (MCHBAR, buffer alignment, misc warnings fixes) - Fixes for newly enabled semaphore code - Geminilake disable framebuffer compression - HSW edp fast modeset fix - IRQ vs RCU race fix nouveau: - Turing modesetting fixes - TU117 support msm: - SDM845 bringup fixes panfrost: - static checker fixes pl111: - spinlock init fix. bridge: - refresh rate register fix for adv7511" * tag 'drm-next-2019-05-16' of git://anongit.freedesktop.org/drm/drm: (36 commits) drm/msm: Upgrade gxpd checks to IS_ERR_OR_NULL drm/msm/dpu: Remove duplicate header drm/pl111: Initialize clock spinlock early drm/msm: correct attempted NULL pointer dereference in debugfs drm/msm: remove resv fields from msm_gem_object struct drm/nouveau: fix duplication of nv50_head_atom struct drm/nouveau/disp/dp: respect sink limits when selecting failsafe link configuration drm/nouveau/core: initial support for boards with TU117 chipset drm/nouveau/core: allow detected chipset to be overridden drm/nouveau/kms/gf119-gp10x: push HeadSetControlOutputResource() mthd when encoders change drm/nouveau/kms/nv50-: fix bug preventing non-vsync'd page flips drm/nouveau/kms/gv100-: fix spurious window immediate interlocks drm/bridge: adv7511: Fix low refresh rate selection drm/panfrost: Add missing _fini() calls in panfrost_device_fini() drm/panfrost: Only put sync_out if non-NULL drm/i915: Seal races between async GPU cancellation, retirement and signaling drm/i915: Fix fastset vs. pfit on/off on HSW EDP transcoder drm/i915/fbc: disable framebuffer compression on GeminiLake drm/amdgpu/psp: move psp version specific function pointers to early_init drm/radeon: prefer lower reference dividers ...
2019-05-14drm/nouveau/disp/dp: respect sink limits when selecting failsafe link ↵Ben Skeggs1-2/+9
configuration Where possible, we want the failsafe link configuration (one which won't hang the OR during modeset because of not enough bandwidth for the mode) to also be supported by the sink. This prevents "link rate unsupported by sink" messages when link training fails. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-05-14drm/nouveau/core: initial support for boards with TU117 chipsetBen Skeggs1-0/+36
Modesetting only, still waiting on ACR/GR firmware from NVIDIA for Turing graphics/compute bring-up. Each subsystem was compared with traces, along with various tests to check that things generally work as they should, and appears compatible enough with the current TU106 code to enable support. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-05-14drm/nouveau/core: allow detected chipset to be overriddenBen Skeggs1-2/+22
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-04-10drm/nouveau/nvkm: mark expected switch fall-throughsGustavo A. R. Silva4-0/+21
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch aims to suppress 29 missing-break-in-switch false positives. Addresses-Coverity-ID: 1456891 ("Missing break in switch") Addresses-Coverity-ID: 1324063 ("Missing break in switch") Addresses-Coverity-ID: 1324063 ("Missing break in switch") Addresses-Coverity-ID: 141432 ("Missing break in switch") Addresses-Coverity-ID: 141433 ("Missing break in switch") Addresses-Coverity-ID: 141434 ("Missing break in switch") Addresses-Coverity-ID: 141435 ("Missing break in switch") Addresses-Coverity-ID: 141436 ("Missing break in switch") Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
2019-02-20drm/nouveau/fault/gp100: expose MaxwellFaultBufferABen Skeggs1-8/+7
This nvclass exposes the replayable fault buffer, which will be used by SVM to manage GPU page faults. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: expose method to determine current contextBen Skeggs3-0/+17
MMU will need access to this info. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: expose fecs methods for pausing ctxswBen Skeggs4-0/+78
MMU will need access to these. v2. Apply fix from Rhys Kidd to send correct FECS method for STOP_CTXSW. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: store fecs/gpccs falcon pointers in substructuresBen Skeggs2-18/+28
Future changes will want to add some additional things here, keep them grouped together. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: move fecs bind_pointer into a functionBen Skeggs3-7/+24
Makes the code somewhat less magic. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: remove some unnecessary reg writesBen Skeggs1-6/+1
This is already done during golden context creation. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: move fecs elpg setup into functionsBen Skeggs1-29/+84
Makes the code somewhat less magic. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: move fecs discover_pm_image_size into a functionBen Skeggs2-8/+21
Makes the code somewhat less magic. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: move fecs discover_zcull_image_size into a functionBen Skeggs2-8/+21
Makes the code somewhat less magic. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: move fecs discover_image_size into a functionBen Skeggs1-8/+21
Makes the code somewhat less magic. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gr/gf100-: move fecs set_watchdog_timeout method into a functionBen Skeggs1-3/+11
Makes the code somewhat less magic. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/disp/gf119-: decode exception reason to human-readable stringBen Skeggs4-12/+26
We also change the error strings to match NVIDIA's naming. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/sec2/tu102-: instantiate SEC2 falconBen Skeggs3-0/+37
Required for ACR. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/sec2: utilise engine PRI address from TOPBen Skeggs3-10/+18
Turing has its SEC2 instance in an alternate location, and this avoids needing to duplicate the code here for it. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/nvdec/tu102-: instantiate NVDEC0 falconBen Skeggs1-0/+3
Required to run VPR scrubber binary as part of secboot. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/nvdec/gp102-: utilise engine PRI address from TOPBen Skeggs1-1/+9
Turing has its NVDEC instances in an alternate location. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/gsp/gv100-: instantiate GSP falconBen Skeggs1-0/+4
We need this for Turing ACR, but it's present from Volta onwards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/core: define GSP subdevBen Skeggs2-0/+3
Exact meaning of the acronym is unknown, but we need this for Turing ACR. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/ce/tu102: rename implementation from tu104Ben Skeggs3-19/+19
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/fifo/tu102: rename implementation from tu104Ben Skeggs7-33/+33
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/disp/tu102: rename implementation from tu104Ben Skeggs7-32/+32
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 00:41:37 +0300