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path: root/drivers/gpu/drm/nouveau/include
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2019-02-20drm/nouveau/top: add function to lookup PRI address for devicesBen Skeggs1-0/+1
Will be using this in upcoming changes to avoid the need for entirely new subdevs to deal with Turing register moves. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/core: define GSP subdevBen Skeggs2-0/+12
Exact meaning of the acronym is unknown, but we need this for Turing ACR. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/ce/tu102: rename implementation from tu104Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/fifo/tu102: rename implementation from tu104Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/disp/tu102: rename implementation from tu104Ben Skeggs2-6/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/fault/tu102: rename implementation from tu104Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/bar/tu102: rename implementation from tu104Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/mmu/tu102: rename implementation from tu104Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/mc/tu102: rename implementation from tu104Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/devinit/tu102: rename implementation from tu104Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/volt/gf117: fix speedo readout registerIlia Mirkin1-0/+1
GF117 appears to use the same register as GK104 (but still with the general Fermi readout mechanism). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108980 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/core: increase maximum number of nvdec instances to 3Ben Skeggs1-3/+4
RTX2070 appears to have 3 copies of the engine. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/ce/tu104: initial supportBen Skeggs2-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/tu104: initial supportBen Skeggs2-0/+2
Various different bits and pieces vs GV100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/disp/tu104: initial supportBen Skeggs2-0/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fault/tu104: initial supportBen Skeggs1-0/+1
New registers. Currently uncertain how exactly to mask fault buffer interrupts. This will likely be corrected at around the same time as the new MC interrupt stuff has been properly figured out and implemented. For the moment, it shouldn't matter too much. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bar/tu104: initial supportBen Skeggs1-0/+1
New registers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/mmu/tu104: initial supportBen Skeggs1-0/+1
New flush method. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/mc/tu104: initial supportBen Skeggs1-0/+1
Things are a bit different here on Turing, and will require further changes yet once I've investigated them more thoroughly. For now though, the existing GP100 code is compatible enough with one small hack to forward on fault buffer interrupts. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/devinit/tu104: initial supportBen Skeggs1-0/+1
The GPU executes DEVINIT itself now, which makes our lives a bit easier. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/core: recognise TU104Ben Skeggs2-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gv100: return work submission token in channel ctor argsBen Skeggs2-1/+20
The token will also contain runlist ID on Turing, so instead expose it as an opaque value from NVKM so the client doesn't need to care. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gk104-: support enabling privileged ce functionsBen Skeggs1-1/+1
Will be used by SVM code to allow direct (without going through MMU) memcpy using the GPU copy engines. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gk104-: return channel instance in ctor argsBen Skeggs1-0/+1
Will be used to match fault buffer entries with a channel. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gf100-: call into BAR to reset BARs after MMU faultBen Skeggs1-0/+2
This is needed for Turing, but we're supposed to wait for completion after re-writing the value on older GPUs anyway. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/imem/nv50: support pinning objects in BAR2 and returning addressBen Skeggs1-0/+2
Various structures are accessed by the GPU through BAR2 for some reason on newer GPUs. This commit makes it more convenient to handle. Will be used for GP100- fault buffers, and GV100- fault method buffers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/tmr: detect stalled gpu timer and break out of waitsBen Skeggs1-10/+18
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bios: translate USB-C connector typeBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bios: translate additional memory typesBen Skeggs2-6/+12
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/core: support multiple nvdec instancesBen Skeggs1-3/+6
Turing GPUs can have more than one. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-10-11drm/nouveau/disp: add a way to configure scrambling/tmds for hdmi 2.0Ilia Mirkin1-1/+4
High pixel clocks are required to use a 40 TMDS divider instead of 10, and even low ones may optionally use scrambling depending on device support. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/nvif: remove const attribute from nvif_mclassNick Desaulniers1-1/+1
Similar to commit 0bf8bf50eddc ("module: Remove const attribute from alias for MODULE_DEVICE_TABLE") Fixes many -Wduplicate-decl-specifier warnings due to the combination of const typeof() of already const variables. Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gv100: initial supportBen Skeggs2-0/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/ce/gv100: initial supportBen Skeggs2-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/fifo/gv100: initial supportBen Skeggs4-0/+26
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/disp/gv100: initial supportBen Skeggs4-0/+32
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/dma/gv100: initial supportBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/fault/gv100: initial supportBen Skeggs1-1/+5
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/mmu/gv100: initial supportBen Skeggs1-0/+1
VEID support hacked in here, as it's the most convenient place for now. Will be refined once it's better understood. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/fb/gv100: initial supportBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/devinit/gv100: initial supportBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/core: recognise gv100Ben Skeggs2-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/core: increase maximum number of copy engines to 9Ben Skeggs1-3/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/kms/nv50-: determine MST support from DP Info TableBen Skeggs1-0/+4
GV100 doesn't support MST, use the information provided in VBIOS tables to detect its presence instead. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/kms: move display class instantiation to libraryBen Skeggs2-0/+28
This function is useful outside of DRM code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gp102-: setup stencil zbcBen Skeggs1-0/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: update r408840 where requiredBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/fifo/gk104-: require explicit runlist selection for channel ↵Ben Skeggs1-16/+2
allocation We didn't used to be aware that runlist/engine IDs weren't the same thing, or that there was such variability in configuration between GPUs. By exposing this information to a client, and giving it explicit control of which runlist it's allocating a channel on, we're able to make better choices. The immediate effect of this is that on GPUs where CE0 is the "GRCE", we will now be allocating a copy engine running asynchronously to GR for BO migrations - as intended. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/fifo/gk104-: support querying engines available on each runlistBen Skeggs3-0/+30
Will be used to improve channel runlist selection. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/fifo/gk104-: allow fault recovery code to be called by other subdevsBen Skeggs2-0/+15
This will be required to support Volta. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-20 15:07:24 +0300