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2020-08-17drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDRSharat Masetty1-8/+17
This patches replaces the previously used static DDR vote and uses dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling GPU frequency. Also since the icc path voting is handled completely in the opp driver, remove the icc_path handle and its usage in the drm driver. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-17drm/msm/gpu: make ringbuffer readonlyRob Clark1-1/+2
The GPU has no business writing into the ringbuffer, let's make it readonly to the GPU. Fixes: 7198e6b03155 ("drm/msm: add a3xx gpu support") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-17drm/msm/adreno: fix updating ring fenceRob Clark1-1/+1
We need to set it to the most recent completed fence, not the most recent submitted. Otherwise we have races where we think we can retire submits that the GPU is not finished with, if the GPU doesn't manage to overwrite the seqno before we look at it. This can show up with hang recovery if one of the submits after the crashing submit also hangs after it is replayed. Fixes: f97decac5f4c ("drm/msm: Support multiple ringbuffers") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-17drm/msm/dpu: fix unitialized variable errorRob Clark1-1/+1
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:817 dpu_crtc_enable() error: uninitialized symbol 'request_bandwidth'. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-17drm/msm/dpu: Fix scale params in plane validationKalyan Thota1-2/+2
Plane validation uses an API drm_calc_scale which will return src/dst value as a scale ratio. when viewing the range on a scale the values should fall in as Upscale ratio < Unity scale < Downscale ratio for src/dst formula Fix the min and max scale ratios to suit the API accordingly. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Tested-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-17drm/msm/dpu: Fix reservation failures in modesetKalyan Thota1-9/+11
In TEST_ONLY commit, rm global_state will duplicate the object and request for new reservations, once they pass then the new state will be swapped with the old and will be available for the Atomic Commit. This patch fixes some of missing links in the resource reservation sequence mentioned above. 1) Creation of duplicate state in test_only commit (Rob) 2) Allocate and release the resources on every modeset. 3) Avoid allocation only when active is false. In a modeset operation, swap state happens well before disable. Hence clearing reservations in disable will cause failures in modeset enable. Allow reservations to be cleared/allocated before swap, such that only newly committed resources are pushed to HW. Changes in v1: - Move the rm release to atomic_check. - Ensure resource allocation and free happens when active is not changed i.e only when mode is changed.(Rob) Changes in v2: - Handle dpu_kms_get_global_state API failure as it may return EDEADLK (swboyd). Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-12Merge drm/drm-next into drm-misc-nextThomas Zimmermann63-1615/+7188
Backmerging drm-next into drm-misc-next for nouveau and panel updates. Resolves a conflict between ttm and nouveau, where struct ttm_mem_res got renamed to struct ttm_resource. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2020-08-08drm: Remove unnecessary drm_panel_attach and drm_panel_detachJoe Perches2-7/+1
These functions are now empty and no longer useful so remove the functions and their uses. Signed-off-by: Joe Perches <joe@perches.com> Cc: Bernard Zhao <bernard@vivo.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org>, Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Icenowy Zheng <icenowy@aosc.io>, Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Robert Chiras <robert.chiras@nxp.com> Cc: dri-devel@lists.freedesktop.org, Cc: linux-kernel@vger.kernel.org Cc: opensource.kernel@vivo.com Signed-off-by: Sam Ravnborg <sam@ravnborg.org> # Fixed build and a few warnings Link: https://patchwork.freedesktop.org/patch/msgid/9e13761020750b1ce2f1fabee23ef6e2a2942882.camel@perches.com
2020-08-06Merge tag 'sched-fifo-2020-08-04' of ↵Linus Torvalds1-12/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull sched/fifo updates from Ingo Molnar: "This adds the sched_set_fifo*() encapsulation APIs to remove static priority level knowledge from non-scheduler code. The three APIs for non-scheduler code to set SCHED_FIFO are: - sched_set_fifo() - sched_set_fifo_low() - sched_set_normal() These are two FIFO priority levels: default (high), and a 'low' priority level, plus sched_set_normal() to set the policy back to non-SCHED_FIFO. Since the changes affect a lot of non-scheduler code, we kept this in a separate tree" * tag 'sched-fifo-2020-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits) sched,tracing: Convert to sched_set_fifo() sched: Remove sched_set_*() return value sched: Remove sched_setscheduler*() EXPORTs sched,psi: Convert to sched_set_fifo_low() sched,rcutorture: Convert to sched_set_fifo_low() sched,rcuperf: Convert to sched_set_fifo_low() sched,locktorture: Convert to sched_set_fifo() sched,irq: Convert to sched_set_fifo() sched,watchdog: Convert to sched_set_fifo() sched,serial: Convert to sched_set_fifo() sched,powerclamp: Convert to sched_set_fifo() sched,ion: Convert to sched_set_normal() sched,powercap: Convert to sched_set_fifo*() sched,spi: Convert to sched_set_fifo*() sched,mmc: Convert to sched_set_fifo*() sched,ivtv: Convert to sched_set_fifo*() sched,drm/scheduler: Convert to sched_set_fifo*() sched,msm: Convert to sched_set_fifo*() sched,psci: Convert to sched_set_fifo*() sched,drbd: Convert to sched_set_fifo*() ...
2020-07-31drm/msm: use kthread_create_worker instead of kthread_runBernard3-15/+8
Use kthread_create_worker to simplify the code and optimise the manager struct: msm_drm_thread. With this change, we could remove struct element (struct task_struct *thread & struct kthread_worker worker), instead, use one point (struct kthread_worker *worker). Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/mdp5: Add MDP5 configuration for SDM636/660Konrad Dybcio1-0/+105
This commit adds support for the MDP5 IP on Snapdragon 636/660. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dsi: Add DSI configuration for SDM660Konrad Dybcio2-0/+22
This also applies to sdm630/636 and their SDA counterparts. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/mdp5: Add MDP5 configuration for SDM630Konrad Dybcio1-0/+93
This commit adds support for the MDP5 IP on Snapdragon 630. The configuration is different from SDM660's, as the latter one has two DSI outputs. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dsi: Add phy configuration for SDM630/636/660Konrad Dybcio3-0/+21
These SoCs make use of the 14nm phy, but at different addresses than other 14nm units. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: add A640/A650 hwcgJonathan Marek3-4/+117
Initialize hardware clock-gating registers on A640 and A650 GPUs. At least for A650, this solves some performance issues. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: hwcg tables in gpulistJonathan Marek3-14/+20
This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add SM8250 to hw catalogJonathan Marek2-0/+109
This brings up basic video mode functionality for SM8250 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add SM8150 to hw catalogJonathan Marek2-0/+149
This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> [fixup max_linewidth warning] Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: intf timing path for displayportJonathan Marek1-5/+15
Calculate the correct timings for displayport, from downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3Jonathan Marek1-18/+2
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845Jonathan Marek3-15/+27
The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it. This also adds separate feature bits for INTF (based on downstream) instead of using CTL feature bit for it, and removes the unnecessary NULL check in the added bind_pingpong_blk function. Fixes: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: move some sspp caps to dpu_capsJonathan Marek3-27/+17
This isn't something that ever changes between planes, so move it to dpu_caps struct. Making this change will allow more re-use in the "SSPP sub blocks config" part of the catalog, in particular when adding support for SM8150 and SM8250 which have different max_linewidth. This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation is not supported on the newest DPU versions. (note that decimation is not implemented, so this changes nothing) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: update UBWC config for sm8150 and sm8250Jonathan Marek6-90/+42
Update the UBWC registers to the right values for sm8150 and sm8250. This removes broken dpu_hw_reset_ubwc, which doesn't work because the "force blk offset to zero to access beginning of register region" hack is copied from downstream, where mapped region starts 0x1000 below what is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250Jonathan Marek1-3/+2
All DPU versions starting from 4.0 use the sdm845 version, so check for that instead of checking each version individually. This chooses the right function for sm8150 and sm8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: set ubwc config for A640 and A650Jonathan Marek1-6/+32
This is required for A640 and A650 to be able to share UBWC-compressed images with other HW such as display, which expect this configuration. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/adreno: un-open-code some packetsRob Clark2-6/+10
Small cleanup, lets not open-code bits/bitfields that are properly defined in the rnndb xml (and therefore have builders in the generated headers) Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: sync generated headersRob Clark18-1200/+5900
We haven't sync'd for a while.. pull in updates to get definitions for some fields in pkt7 payloads. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: add build_bw_table for A640/A650Jonathan Marek1-0/+74
This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was working, but this is required for A650 to work. Eventually the bw table should be filled by querying the interconnect driver for each BW in the dts, but use these dummy tables for now. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: fix crashstate capture for A650Jonathan Marek3-11/+31
A650 has a separate RSCC region, so dump RSCC registers separately, reading them from the RSCC base. Without this change a GPU hang will cause a system reset if CONFIG_DEV_COREDUMP is enabled. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Quiet error during failure in optional resource mappings.Eric Anholt3-6/+22
We don't expect to find vbif_nrt or regdma on sdm845, but were clogging up dmesg with errors about it. Signed-off-by: Eric Anholt <eric@anholt.net> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Garbage collect unused resource _len fields.Eric Anholt3-31/+0
Nothing was using the lengths of these ioremaps. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: fix/enable 6bpc dither with split-lmRob Clark2-12/+13
If split-lm is used (for ex, on sdm845), we can have multiple ping- pongs, but only a single phys encoder. We need to configure dithering on each of them. Signed-off-by: Rob Clark <robdclark@chromium.org> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm: msm: a6xx: fix gpu failure after system resumeAkhil P Oommen1-8/+10
On targets where GMU is available, GMU takes over the ownership of GX GDSC during its initialization. So, move the refcount-get on GX PD before we initialize the GMU. This ensures that nobody can collapse the GX GDSC once GMU owns the GX GDSC. This patch fixes some GMU OOB errors seen during GPU wake up during a system resume. Reported-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: dsi: Use OPP API to set clk/perf stateRajendra Nayak1-2/+25
On SDM845 and SC7180 DSI needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. dev_pm_opp_set_rate() is designed to be equivalent to clk_set_rate() for devices without an OPP table, hence the change works fine on devices/platforms which only need to set a clock rate. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: Use OPP API to set clk/perf stateRajendra Nayak3-2/+32
On some qualcomm platforms DPU needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: ratelimit crtc event overflow errorRob Clark1-1/+1
This can happen a lot when things go pear shaped. Lets not flood dmesg when this happens. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm: msm: a6xx: send opp instead of a frequencySharat Masetty4-45/+52
This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Fix a null pointer access in msm_gem_shrinker_count()Akhil P Oommen1-15/+21
Adding an msm_gem_object object to the inactive_list before completing its initialization is a bad idea because shrinker may pick it up from the inactive_list. Fix this by making sure that the initialization is complete before moving the msm_obj object to the inactive list. This patch fixes the below error: [10027.553044] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000068 [10027.573305] Mem abort info: [10027.590160] ESR = 0x96000006 [10027.597905] EC = 0x25: DABT (current EL), IL = 32 bits [10027.614430] SET = 0, FnV = 0 [10027.624427] EA = 0, S1PTW = 0 [10027.632722] Data abort info: [10027.638039] ISV = 0, ISS = 0x00000006 [10027.647459] CM = 0, WnR = 0 [10027.654345] user pgtable: 4k pages, 39-bit VAs, pgdp=00000001e3a6a000 [10027.672681] [0000000000000068] pgd=0000000198c31003, pud=0000000198c31003, pmd=0000000000000000 [10027.693900] Internal error: Oops: 96000006 [#1] PREEMPT SMP [10027.738261] CPU: 3 PID: 214 Comm: kswapd0 Tainted: G S 5.4.40 #1 [10027.745766] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT) [10027.752472] pstate: 80c00009 (Nzcv daif +PAN +UAO) [10027.757409] pc : mutex_is_locked+0x14/0x2c [10027.761626] lr : msm_gem_shrinker_count+0x70/0xec [10027.766454] sp : ffffffc011323ad0 [10027.769867] x29: ffffffc011323ad0 x28: ffffffe677e4b878 [10027.775324] x27: 0000000000000cc0 x26: 0000000000000000 [10027.780783] x25: ffffff817114a708 x24: 0000000000000008 [10027.786242] x23: ffffff8023ab7170 x22: 0000000000000001 [10027.791701] x21: ffffff817114a080 x20: 0000000000000119 [10027.797160] x19: 0000000000000068 x18: 00000000000003bc [10027.802621] x17: 0000000004a34210 x16: 00000000000000c0 [10027.808083] x15: 0000000000000000 x14: 0000000000000000 [10027.813542] x13: ffffffe677e0a3c0 x12: 0000000000000000 [10027.819000] x11: 0000000000000000 x10: ffffff8174b94340 [10027.824461] x9 : 0000000000000000 x8 : 0000000000000000 [10027.829919] x7 : 00000000000001fc x6 : ffffffc011323c88 [10027.835373] x5 : 0000000000000001 x4 : ffffffc011323d80 [10027.840832] x3 : ffffffff0477b348 x2 : 0000000000000000 [10027.846290] x1 : ffffffc011323b68 x0 : 0000000000000068 [10027.851748] Call trace: [10027.854264] mutex_is_locked+0x14/0x2c [10027.858121] msm_gem_shrinker_count+0x70/0xec [10027.862603] shrink_slab+0xc0/0x4b4 [10027.866187] shrink_node+0x4a8/0x818 [10027.869860] kswapd+0x624/0x890 [10027.873097] kthread+0x11c/0x12c [10027.876424] ret_from_fork+0x10/0x18 [10027.880102] Code: f9000bf3 910003fd aa0003f3 d503201f (f9400268) [10027.886362] ---[ end trace df5849a1a3543251 ]--- [10027.891518] Kernel panic - not syncing: Fatal exception Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add support for dither block in displayKalyan Thota3-9/+121
This change enables dither block for primary interface in display. Enabled for 6bpc in the current version. Changes in v1: - Remove redundant error checks (Rob). Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/adreno: fix gpu probe if no interconnect-namesRob Clark1-8/+10
If there is no interconnect-names, but there is an interconnects property, then of_icc_get(dev, "gfx-mem"); would return an error rather than NULL. Also, if there is no interconnect-names property, there will never be a ocmem path. But of_icc_get(dev, "ocmem") would return -EINVAL instead of -ENODATA. Just don't bother trying in this case. v2: explicity check for interconnect-names property Fixes: 08af4769c7d2 ("drm/msm: handle for EPROBE_DEFER for of_icc_get") Fixes: 00bb9243d346 ("drm/msm/gpu: add support for ocmem interconnect path") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-30drm/msm/dpu: enumerate second cursor pipe for external interfaceKalyan Thota1-6/+6
Setup an RGB HW pipe as cursor which can be used on secondary interface. For SC7180 2 HW pipes are enumerated as cursors 1 - primary interface 2 - secondary interface Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-30drm/msm/dpu: ensure device suspend happens during PM sleepKalyan Thota3-36/+35
"The PM core always increments the runtime usage counter before calling the ->suspend() callback and decrements it after calling the ->resume() callback" DPU and DSI are managed as runtime devices. When suspend is triggered, PM core adds a refcount on all the devices and calls device suspend, since usage count is already incremented, runtime suspend was not getting called and it kept the clocks on which resulted in target not entering into XO shutdown. Add changes to force suspend on runtime devices during pm sleep. Changes in v1: - Remove unnecessary checks in the function _dpu_kms_disable_dpu (Rob Clark). Changes in v2: - Avoid using suspend_late to reset the usagecount as suspend_late might not be called during suspend call failures (Doug). Changes in v3: - Use force suspend instead of managing device usage_count via runtime put and get API's to trigger callbacks (Doug). Changes in v4: - Check the return values of pm_runtime_force_suspend and pm_runtime_force_resume API's and pass appropriately (Doug). Changes in v5: - With v4 patch, test cycle has uncovered issues in device resume. On bubs: cmd tx failures were seen as SW is sending panel off commands when the dsi resources are turned off. Upon suspend, DRM driver will issue a NULL composition to the dpu, followed by turning off all the HW blocks. v5 changes will serialize the NULL commit and resource unwinding by handling them under PM prepare and PM complete phases there by ensuring that clks are on when panel off commands are being processed. Changes in v6: - Use drm_mode_config_helper_suspend/resume() instead of legacy API drm_atomic_helper_suspend/resume() (Doug). Trigger runtime callbacks from the suspend/resume call to turn off the resources. Changes in v7: - Add "__maybe_unused" to the functions to avoid compilation failures. Cleanup unnecessary configs (Doug). Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-30drm/msm: handle for EPROBE_DEFER for of_icc_getJonathan Marek1-27/+38
Check for errors instead of silently not using icc if the msm driver probes before the interconnect driver. Allow ENODATA for ocmem path, as it is optional and this error is returned when "gfx-mem" path is provided but not "ocmem". Because msm_gpu_cleanup assumes msm_gpu_init has been called, the icc path init needs to be after msm_gpu_init for the error path to work. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-30drm/msm: reset devfreq freq_table/max_state before devfreq_add_deviceJonathan Marek1-0/+4
These never get set back to 0 when probing fails, so an attempt to probe again results in broken behavior. Fix the problem by setting thse to zero before they are used. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-30drm/msm: fix unbalanced pm_runtime_enable in adreno_gpu_{init, cleanup}Jonathan Marek1-0/+3
adreno_gpu_init calls pm_runtime_enable, so adreno_gpu_cleanup needs to call pm_runtime_disable. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-24Merge v5.8-rc6 into drm-nextDave Airlie9-15/+21
I've got a silent conflict + two trees based on fixes to merge. Fixes a silent merge with amdgpu Signed-off-by: Dave Airlie <airlied@redhat.com>
2020-07-02drm/atomic-helper: reset vblank on crtc resetDaniel Vetter1-2/+0
Only when vblanks are supported ofc. Some drivers do this already, but most unfortunately missed it. This opens up bugs after driver load, before the crtc is enabled for the first time. syzbot spotted this when loading vkms as a secondary output. Given how many drivers are buggy it's best to solve this once and for all in shared helper code. Aside from moving the few existing calls to drm_crtc_vblank_reset into helpers (i915 doesn't use helpers, so keeps its own) I think the regression risk is minimal: atomic helpers already rely on drivers calling drm_crtc_vblank_on/off correctly in their hooks when they support vblanks. And driver that's failing to handle vblanks after this is missing those calls already, and vblanks could only work by accident when enabling a CRTC for the first time right after boot. Big thanks to Tetsuo for helping track down what's going wrong here. There's only a few drivers which already had the necessary call and needed some updating: - komeda, atmel and tidss also needed to be changed to call __drm_atomic_helper_crtc_reset() intead of open coding it - tegra and msm even had it in the same place already, just code motion, and malidp already uses __drm_atomic_helper_crtc_reset(). - Laurent noticed that rcar-du and omap open-code their crtc reset and hence would actually be broken by this patch now. So fix them up by reusing the helpers, which brings the drm_crtc_vblank_reset() back. Only call left is in i915, which doesn't use drm_mode_config_reset, but has its own fastboot infrastructure. So that's the only case where we actually want this in the driver still. I've also reviewed all other drivers which set up vblank support with drm_vblank_init. After the previous patch fixing mxsfb all atomic drivers do call drm_crtc_vblank_on/off as they should, the remaining drivers are either legacy kms or legacy dri1 drivers, so not affected by this change to atomic helpers. v2: Use the drm_dev_has_vblank() helper. v3: Laurent pointed out that omap and rcar-du used drm_crtc_vblank_off instead of drm_crtc_vblank_reset. Adjust them too. v4: Laurent noticed that rcar-du and omap open-code their crtc reset and hence would actually be broken by this patch now. So fix them up by reusing the helpers, which brings the drm_crtc_vblank_reset() back. v5: also mention rcar-du and ompadrm in the proper commit message above (Laurent). Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Maxime Ripard <mripard@kernel.org> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb Reported-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp> Reported-by: syzbot+0871b14ca2e2fb64f6e3@syzkaller.appspotmail.com Cc: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp> Cc: "James (Qian) Wang" <james.qian.wang@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Mihail Atanassov <mihail.atanassov@arm.com> Cc: Brian Starkey <brian.starkey@arm.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Emil Velikov <emil.velikov@collabora.com> Cc: zhengbin <zhengbin13@huawei.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-tegra@vger.kernel.org Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200612160056.2082681-1-daniel.vetter@ffwll.ch
2020-07-01Merge tag 'drm-msm-fixes-2020-06-25' of ↵Dave Airlie9-15/+21
https://gitlab.freedesktop.org/drm/msm into drm-fixes A few fixes, mostly fallout from the address space refactor and dpu color processing. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/ <CAF6AEGv0SSXArdYs=mOLqJPJdkvk8CpxaJGecqgbOGazQ2n5og@mail.gmail.com
2020-06-24Merge tag 'drm-misc-next-2020-06-19' of ↵Dave Airlie14-64/+37
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.9: UAPI Changes: - Add DRM_MODE_TYPE_USERDEF for video modes specified in cmdline. Cross-subsystem Changes: - Assorted devicetree binding updates. - Add might_sleep() to dma_fence_wait(). - Fix fbdev's get_user_pages_fast() handling, and use pin_user_pages. - Small cleanup with IS_BUILTIN in video/fbdev drivers. - Fix video/hdmi coding style for infoframe size. Core Changes: - Silence vblank output during init. - Fix DP-MST corruption during send msg timeout. - Clear leak in drm_gem_objecs_lookup(). - Make newlines work with force connector attribute. - Fix module refcounting error in drm_encoder_slave, and use new i2c api. - Header fix for drm_managed.c - More struct_mutex removal for !legacy drivers: - Remove gem_free_object() - Removal of drm_gem_object_put_unlocked(). - Show current->comm alongside pid in debug printfs. - Add drm_client_modeset_check() + drm_client_framebuffer_flush(). - Replace drm_fb_swab16 with drm_fb_swap that also supports 32-bits. - Remove mode->vrefresh, and compactify drm_display_mode. - Use drm_* macros for logging and warnings. - Add WARN when drm_gem_get_pages is used on a private obj. - Handle importing and imported dmabuf better in shmem helpers. - Small fix for drm/mm hole size comparison, and remove invalid entry optimization. - Add a drm/mm selftest. - Set DSI connector type for DSI panels. - Assorted small fixes and documentation updates. - Fix DDI I2C device registration for MST ports, and flushing on destroy. - Fix master_set return type, used by vmwgfx. - Make the drm_set/drop_master ioctl symmetrical. Driver Changes: Allow iommu in the sun4i driver and use it for sun8i. - Simplify backlight lookup for omap, amba-clcd and tilcdc. - Hold reg_lock for rockchip. - Add support for bridge gpio and lane reordering + polarity to ti-sn65dsi86, and fix clock choice. - Small assorted fixes to tilcdc, vc4, i915, omap, fbdev/sm712fb, fbdev/pxafb, console/newport_con, msm, virtio, udl, malidp, hdlcd, bridge/ti-sn65dsi86, panfrost. - Remove hw cursor support for mgag200, and use simple kms helper + shmem helpers. - Add support for KOE Allow iommu in the sun4i driver and use it for sun8i. - Simplify backlight lookup for omap, amba-clcd and tilcdc. - Hold reg_lock for rockchip. - Add support for bridge gpio and lane reordering + polarity to ti-sn65dsi86, and fix clock choice. - Small assorted fixes to tilcdc, vc4 (multiple), i915. - Remove hw cursor support for mgag200, and use simple kms helper + shmem helpers. - Add support for KOE TX26D202VM0BWA panel. - Use GEM CMA functions in arc, arm, atmel-hlcdc, fsi-dcu, hisilicon, imx, ingenic, komeda, malidp, mcde, meson, msxfb, rcar-du, shmobile, stm, sti, tilcdc, tve200, zte. - Remove gem_print_info. - Improve gem_create_object_helper so udl can use shmem helpers. - Convert vc4 dt bindings to schemas, and add clock properties. - Device initialization cleanups for mgag200. - Add a workaround to fix DP-MST short pulses handling on broken hardware in i915. - Allow build test compiling arm drivers. - Use managed pci functions in mgag200 and ast. - Use dev_groups in malidp. - Add per pixel alpha support for PX30 VOP in rockchip. - Silence deferred probe logs in panfrost. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/001cd9a6-405d-4e29-43d8-354f53ae4e8b@linux.intel.com
2020-06-22drm/msm: Fix up the rest of the messed up address sizesJordan Crouse5-5/+5
msm_gem_address_space_create() changed to take a start/length instead of a start/end for the iova space but all of the callers were just cut and pasted from the old usage. Most of the mistakes have been fixed up so just catch up the rest. Fixes: ccac7ce373c1 ("drm/msm: Refactor address space initialization") Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-19 10:23:45 +0300