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2020-09-15drm/msm: Get rid of the REG_ADRENO offsetsJordan Crouse7-234/+178
As newer GPU families are added it makes less sense to maintain a "generic" version functions for older families. Move adreno_submit() and get_rptr() into the target specific code for a2xx, a3xx and a4xx. Add a parameter to adreno_flush to pass the target specific WPTR register instead of relying on the generic register. All of this gets rid of the last of the REG_ADRENO offsets so remove all all the register definitions and infrastructure. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm: a6xx: Use WHERE_AM_I for eligible targetsJordan Crouse2-3/+93
Support the WHERE_AM_I opcode for the A618, A630 and A640 GPUs if the microcode supports it. The WHERE_AM_I opcode allows the RPTR shadow to be updated in priviliged memory which protects the shadow from being read or written from user submissions. A650 already supports extended APRIV have built in hardware support for to access privilged memory from the CP and can go back to using the hardware RPTR shadow feature. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm: Allow a5xx to mark the RPTR shadow as privilegedJordan Crouse7-13/+109
Newer microcode versions have support for the CP_WHERE_AM_I opcode which allows the RPTR shadow memory to be marked as privileged to protect it from corruption. Move the RPTR shadow into its own buffer and protect it it if the current microcode version supports the new feature. We can also re-enable preemption for those targets that support CP_WHERE_AM_I. Start out by preemptively assuming that we can enable preemption and disable it in a5xx_hw_init if the microcode version comes back as too old. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-14Merge drm/drm-next into drm-misc-nextMaxime Ripard21-65/+187
Paul Cercueil needs some patches in -rc5 to apply new patches for ingenic properly. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-09-12drm/msm: Show process names in gem_describeRob Clark6-9/+34
In $debugfs/gem we already show any vma(s) associated with an object. Also show process names if the vma's address space is a per-process address space. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm/a6xx: Add support for per-instance pagetablesJordan Crouse3-0/+64
Add support for using per-instance pagetables if all the dependencies are available. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Akhil P Oommen <akhilpo@codeaurora.org>
2020-09-12drm/msm: Add support for private address space instancesJordan Crouse5-6/+48
Add support for allocating private address space instances. Targets that support per-context pagetables should implement their own function to allocate private address spaces. The default will return a pointer to the global address space. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm: Add support to create a local pagetableJordan Crouse4-3/+215
Add support to create a io-pgtable for use by targets that support per-instance pagetables. In order to support per-instance pagetables the GPU SMMU device needs to have the qcom,adreno-smmu compatible string and split pagetables enabled. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm: Set the global virtual address range from the IOMMU domainJordan Crouse2-2/+18
Use the aperture settings from the IOMMU domain to set up the virtual address range for the GPU. This allows us to transparently deal with IOMMU side features (like split pagetables). Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm: Drop context arg to gpu->submit()Jordan Crouse7-25/+17
Now that we can get the ctx from the submitqueue, the extra arg is redundant. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> [split out of previous patch to reduce churny noise] Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm: Add a context pointer to the submitqueueJordan Crouse6-4/+30
Each submitqueue is attached to a context. Add a pointer to the context to the submitqueue at create time and refcount it so that it stays around through the life of the queue. Co-developed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm: Set adreno_smmu as gpu's drvdataRob Clark3-4/+6
This will be populated by adreno-smmu, to provide a way for coordinating enabling/disabling TTBR0 translation. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm/gpu: Add dev_to_gpu() helperRob Clark3-9/+12
In a later patch, the drvdata will not directly be 'struct msm_gpu *', so add a helper to reduce the churn. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm: Remove dangling submitqueue referencesRob Clark1-1/+3
Currently it doesn't matter, since we free the ctx immediately. But when we start refcnt'ing the ctx, we don't want old dangling list entries to hang around. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12drm/msm/a6xx: fix a potential overflow issueZhenzhong Duan1-1/+1
It's allocating an array of a6xx_gpu_state_obj structure rathor than its pointers. This patch fix it. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-12drm/msm/adreno: fix probe without iommuLuca Weiss1-2/+8
The function iommu_domain_alloc returns NULL on platforms without IOMMU such as msm8974. This resulted in PTR_ERR(-ENODEV) being assigned to gpu->aspace so the correct code path wasn't taken. Fixes: ccac7ce373c1 ("drm/msm: Refactor address space initialization") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-12drm/msm/gpu: Add suspend/resume tracepointsRob Clark3-0/+32
Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-12drm/msm/dsi: add support for 7nm DSI PHY/PLLJonathan Marek10-0/+1714
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250. Implementation is based on 10nm driver, but updated based on the downstream 7nm driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-12drm/msm/dsi: add DSI config for sm8150 and sm8250Jonathan Marek2-1/+6
This allows DSI driver to work with sm8150 and sm8250. The sdm845 config is re-used as the config is the same. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-12drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_timingJonathan Marek1-2/+0
The clk_pre/clk_post values in shared_timings are used instead, and these are unused. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-12drm/msm: Drop local dma_parmsRobin Murphy1-9/+1
Since commit 9495b7e92f71 ("driver core: platform: Initialize dma_parms for platform devices"), struct platform_device already provides a dma_parms structure, so we can save allocating another one. Also the DMA segment size is simply a size, not a bitmask. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-10drm: msm: fix common struct sg_table related issuesMarek Szyprowski3-17/+13
The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function returns the number of the created entries in the DMA address space. However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and dma_unmap_sg must be called with the original number of the entries passed to the dma_map_sg(). struct sg_table is a common structure used for describing a non-contiguous memory buffer, used commonly in the DRM and graphics subsystems. It consists of a scatterlist with memory pages and DMA addresses (sgl entry), as well as the number of scatterlist entries: CPU pages (orig_nents entry) and DMA mapped pages (nents entry). It turned out that it was a common mistake to misuse nents and orig_nents entries, calling DMA-mapping functions with a wrong number of entries or ignoring the number of mapped entries returned by the dma_map_sg() function. To avoid such issues, lets use a common dma-mapping wrappers operating directly on the struct sg_table objects and use scatterlist page iterators where possible. This, almost always, hides references to the nents and orig_nents entries, making the code robust, easier to follow and copy/paste safe. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Rob Clark <robdclark@gmail.com>
2020-09-10drm/msm: Convert shrinker msgs to tracepointsRob Clark2-2/+29
This reduces the spam in dmesg when we start hitting the shrinker, and replaces it with something we can put on a timeline while profiling or debugging system issues. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2020-09-10drm/msm/gpu: Add GPU freq_change tracesRob Clark3-0/+36
Technically the GMU specific one is a bit redundant, but it was useful to track down a bug. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
2020-09-10drm/msm: Drop debug print in _dpu_crtc_setup_lm_bounds()Stephen Boyd1-2/+0
This function is called quite often if you have a blinking cursor on the screen, hello page flip. Let's drop this debug print here because it means enabling the print via the module parameter starts to spam the debug console. Cc: Abhinav Kumar <abhinavk@codeaurora.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Sean Paul <seanpaul@chromium.org> Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-10drm/msm: Avoid div-by-zero in dpu_crtc_atomic_check()Stephen Boyd1-3/+5
The cstate->num_mixers member is only set to a non-zero value once dpu_encoder_virt_mode_set() is called, but the atomic check function can be called by userspace before that. Let's avoid the div-by-zero here and inside _dpu_crtc_setup_lm_bounds() by skipping this part of the atomic check if dpu_encoder_virt_mode_set() hasn't been called yet. This fixes an UBSAN warning: UBSAN: Undefined behaviour in drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:860:31 division by zero CPU: 7 PID: 409 Comm: frecon Tainted: G S 5.4.31 #128 Hardware name: Google Trogdor (rev0) (DT) Call trace: dump_backtrace+0x0/0x14c show_stack+0x20/0x2c dump_stack+0xa0/0xd8 __ubsan_handle_divrem_overflow+0xec/0x110 dpu_crtc_atomic_check+0x97c/0x9d4 drm_atomic_helper_check_planes+0x160/0x1c8 drm_atomic_helper_check+0x54/0xbc drm_atomic_check_only+0x6a8/0x880 drm_atomic_commit+0x20/0x5c drm_atomic_helper_set_config+0x98/0xa0 drm_mode_setcrtc+0x308/0x5dc drm_ioctl_kernel+0x9c/0x114 drm_ioctl+0x2ac/0x4b0 drm_compat_ioctl+0xe8/0x13c __arm64_compat_sys_ioctl+0x184/0x324 el0_svc_common+0xa4/0x154 el0_svc_compat_handler+0x Cc: Abhinav Kumar <abhinavk@codeaurora.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Sean Paul <seanpaul@chromium.org> Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-10drm/msm/dpu: clean up some impossibilitiesRob Clark1-78/+13
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-09-10drm/msm/dpu: move vblank events to complete_commit()Rob Clark1-1/+1
We could get a vblank event racing with the current atomic commit, resulting in sending the pageflip event to userspace early, causing tearing. On the other hand, complete_commit() ensures that the pending flush is complete. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-09-09drm: allow limiting the scatter list size.Gerd Hoffmann2-2/+2
Add drm_device argument to drm_prime_pages_to_sg(), so we can call dma_max_mapping_size() to figure the segment size limit and call into __sg_alloc_table_from_pages() with the correct limit. This fixes virtio-gpu with sev. Possibly it'll fix other bugs too given that drm seems to totaly ignore segment size limits so far ... v2: place max_segment in drm driver not gem object. v3: move max_segment next to the other gem fields. v4: just use dma_max_mapping_size(). Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20200907112425.15610-2-kraxel@redhat.com
2020-09-09Backmerge drm-fixes merge into drm-nextDave Airlie11-37/+85
Commit '6f6a73c8b715d595977774d48450a734297ab21f' from Linus' tree The fixes reverts cause a bit of a conflict pain with intel next, start fixing it up here. Signed-off-by: Dave Airlie <airlied@redhat.com>
2020-09-08Merge tag 'drm-msm-fixes-2020-09-04' of ↵Dave Airlie11-37/+85
https://gitlab.freedesktop.org/drm/msm into drm-fixes A few fixes for a potential RPTR corruption issue. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/ <CAF6AEGvnr6Nhz2J0sjv2G+j7iceVtaDiJDT8T88uW6jiBfOGKQ@mail.gmail.com
2020-09-08Merge tag 'v5.9-rc4' into drm-nextDave Airlie14-30/+104
Backmerge 5.9-rc4 as there is a nasty qxl conflict that needs to be resolved. Signed-off-by: Dave Airlie <airlied@redhat.com>
2020-09-04drm/msm/adreno: remove return value of function XX_printBernard Zhao1-14/+7
XX_print like pfp_print/me_print/meq_print/roq_print are just used in file a5xx_debugfs.c. And these function always return 0, this return value is meaningless. This change is to make the code a bit more readable. Signed-off-by: Bernard Zhao <bernard@vivo.com> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-04drm/msm: drop cache sync hackRob Clark1-14/+4
Now that it isn't causing problems to use dma_map/unmap, we can drop the hack of using dma_sync in certain cases. Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-04drm/msm/mdp5: Remove unused downstream bus scaling apisSai Prakash Ranjan2-92/+0
MSM bus scaling has moved on to use interconnect framework and downstream bus scaling apis are not present anymore. Remove them as they are nop anyways in the current code, no functional change. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-04drm/msm/mdp4: Remove unused downstream bus scaling apisSai Prakash Ranjan3-111/+0
MSM bus scaling has moved on to use interconnect framework and downstream bus scaling apis are not present anymore. Remove them as they are nop anyways in the current code, no functional change. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-04drm/msm/dpu: add support for clk and bw scaling for displayKalyan Thota8-23/+233
This change adds support to scale src clk and bandwidth as per composition requirements. Interconnect registration for bw has been moved to mdp device node from mdss to facilitate the scaling. Changes in v1: - Address armv7 compilation issues with the patch (Rob) Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-04drm/msm: Disable the RPTR shadowJordan Crouse6-27/+43
Disable the RPTR shadow across all targets. It will be selectively re-enabled later for targets that need it. Cc: stable@vger.kernel.org Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-04drm/msm: Disable preemption on all 5xx targetsJordan Crouse1-1/+2
Temporarily disable preemption on a5xx targets pending some improvements to protect the RPTR shadow from being corrupted. Cc: stable@vger.kernel.org Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-04drm/msm: Enable expanded apriv support for a650Jordan Crouse4-4/+19
a650 supports expanded apriv support that allows us to map critical buffers (ringbuffer and memstore) as as privileged to protect them from corruption. Cc: stable@vger.kernel.org Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-04drm/msm: Split the a5xx preemption recordJordan Crouse2-5/+21
The main a5xx preemption record can be marked as privileged to protect it from user access but the counters storage needs to be remain unprivileged. Split the buffers and mark the critical memory as privileged. Cc: stable@vger.kernel.org Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-28Merge tag 'drm-fixes-2020-08-28' of git://anongit.freedesktop.org/drm/drmLinus Torvalds12-25/+99
Pull drm fixes from Dave Airlie: "As expected a bit of an rc3 uptick, amdgpu and msm are the main ones, one msm patch was from the merge window, but had dependencies and we dropped it until the other tree had landed. Otherwise it's a couple of fixes for core, and etnaviv, and single i915, exynos, omap fixes. I'm still tracking the Sandybridge gpu relocations issue, if we don't see much movement I might just queue up the reverts. I'll talk to Daniel next week once he's back from holidays. core: - Take modeset bkl for legacy drivers dp_mst: - Allow null crtc in dp_mst i915: - Fix command parser desc matching with masks amdgpu: - Misc display fixes - Backlight fixes - MPO fix for DCN1 - Fixes for Sienna Cichlid - Fixes for Navy Flounder - Vega SW CTF fixes - SMU fix for Raven - Fix a possible overflow in INFO ioctl - Gfx10 clockgating fix msm: - opp/bw scaling patch followup - frequency restoring fux - vblank in atomic commit fix - dpu modesetting fixes - fencing fix etnaviv: - scheduler interaction fix - gpu init regression fix exynos: - Just drop __iommu annotation to fix sparse warning omap: - locking state fix" * tag 'drm-fixes-2020-08-28' of git://anongit.freedesktop.org/drm/drm: (41 commits) drm/amd/display: Fix memleak in amdgpu_dm_mode_config_init drm/amdgpu: disable runtime pm for navy_flounder drm/amd/display: Retry AUX write when fail occurs drm/amdgpu: Fix buffer overflow in INFO ioctl drm/amd/powerplay: Fix hardmins not being sent to SMU for RV drm/amdgpu: use MODE1 reset for navy_flounder by default drm/amd/pm: correct the thermal alert temperature limit settings drm/amdgpu: add asd fw check before loading asd drm/amd/display: Keep current gain when ABM disable immediately drm/amd/display: Fix passive dongle mistaken as active dongle in EDID emulation drm/amd/display: Revert HDCP disable sequence change drm/amd/display: Send DISPLAY_OFF after power down on boot drm/amdgpu/gfx10: refine mgcg setting drm/amd/pm: correct Vega20 swctf limit setting drm/amd/pm: correct Vega12 swctf limit setting drm/amd/pm: correct Vega10 swctf limit setting drm/amd/pm: set VCN pg per instances drm/amd/pm: enable run_btc callback for sienna_cichlid drivers: gpu: amd: Initialize amdgpu_dm_backlight_caps object to 0 in amdgpu_dm_update_backlight_caps drm/amd/display: Reject overlay plane configurations in multi-display scenarios ...
2020-08-24treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva4-5/+5
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
2020-08-22drm/msm/a6xx: fix frequency not always being restored on GMU resumeJonathan Marek1-0/+1
The patch reorganizing the set_freq function made it so the gmu resume doesn't always set the frequency, because a6xx_gmu_set_freq() exits early when the frequency hasn't been changed. Note this always happens when resuming GMU after recovering from a hang. Use a simple workaround to prevent this from happening. Fixes: 1f60d11423db ("drm: msm: a6xx: send opp instead of a frequency") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-22drm/msm/a6xx: add module param to enable debugbus snapshotRob Clark3-1/+8
For production devices, the debugbus sections will typically be fused off and empty in the gpu device coredump. But since this may contain data like cache contents, don't capture it by default. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-22drm/msm/a6xx: fix crashdec section name typoRob Clark1-1/+1
Backport note: maybe wait some time for the crashdec MR[1] to look for both the old typo'd name and the corrected name to land in mesa 20.2 [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6242 Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-22drm/msm/a6xx: fix gmu start on newer firmwareDmitry Baryshkov1-1/+11
New Qualcomm firmware has changed a way it reports back the 'started' event. Support new register values. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-22drm/msm: enable vblank during atomic commitsRob Clark1-0/+36
This has roughly the same effect as drm_atomic_helper_wait_for_vblanks(), basically just ensuring that vblank accounting is enabled so that we get valid timestamp/seqn on pageflip events. Signed-off-by: Rob Clark <robdclark@chromium.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-18drm/msm: add shutdown support for display platform_driverKrishna Manikandan1-0/+8
Define shutdown callback for display drm driver, so as to disable all the CRTCS when shutdown notification is received by the driver. This change will turn off the timing engine so that no display transactions are requested while mmu translations are getting disabled during reboot sequence. Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Changes in v2: - Remove NULL check from msm_pdev_shutdown (Stephen Boyd) - Change commit text to reflect when this issue was uncovered (Sai Prakash Ranjan) Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-08-18Merge v5.9-rc1 into drm-misc-nextMaxime Ripard1-12/+1
Sam needs 5.9-rc1 to have dev_err_probe in to merge some patches. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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