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path: root/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
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2023-06-10drm/msm/adreno: Add Adreno A690 supportBjorn Andersson1-0/+33
Introduce support for the Adreno A690, found in Qualcomm SC8280XP. Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/540335/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2022-07-06drm/msm/adreno: Add A619 supportKonrad Dybcio1-2/+63
Add support for the Adreno 619 GPU, as found in Snapdragon 690 (SM6350), 480 (SM4350) and 750G (SM7225). Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/487588/ Link: https://lore.kernel.org/r/20220528160353.157870-2-konrad.dybcio@somainline.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-11-30drm/msm/gpu: Also snapshot GMU HFI bufferRob Clark1-0/+10
This also includes a history of start index of the last 8 messages on each queue, since parsing backwards to decode recently sent HFI messages is hard(ish). Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20211124214151.1427022-9-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-11drm/msm: Add adreno_is_a640_family()Rob Clark1-1/+1
Combine adreno_is_a640() and adreno_is_a680(). Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20210807163019.379003-1-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-07drm: msm: Add 680 gpu to the adreno gpu listBjorn Andersson1-1/+1
This patch adds a Adreno 680 entry to the gpulist. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210725032002.3961691-1-bjorn.andersson@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-07-31drm/msm/a6xx: Add support for Adreno 7c Gen 3 gpuAkhil P Oommen1-0/+32
This patch adds support for the gpu found in the Snapdragon 7c Gen 3 compute platform. This gpu is similar to the exisiting a660 gpu with minor delta in the programing sequence. As the Adreno GPUs are moving away from a numeric chipid based naming scheme to a string, it was decided to use 0x06030500 as the chip id of this gpu to communicate to the userspace driver. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210730011945.v4.3.I610377db0934b6b7deda532ec2bf786a02c38c01@changeid Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/a6xx: add support for Adreno 660 GPUJonathan Marek1-0/+33
Add adreno_is_{a660,a650_family} helpers and convert update existing adreno_is_a650 usage based on downstream driver's logic (changing into adreno_is_a650_family or adding adreno_is_a660). And add the remaining changes required for A660, again based on the downstream driver: missing GMU allocations, additional register init, dummy hfi BW table, cp protect list, entry in gpulist table, hwcg table, updated a6xx_ucode_check_version check. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210608172808.11803-6-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: add build_bw_table for A640/A650Jonathan Marek1-0/+74
This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was working, but this is required for A650 to work. Eventually the bw table should be filled by querying the interconnect driver for each BW in the dts, but use these dummy tables for now. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-05-22drm/msm/a6xx: a6xx_hfi_send_start() can be statickbuild test robot1-2/+2
Fixes: 8167e6fa76c8 ("drm/msm/a6xx: HFI v2 for A640 and A650") Signed-off-by: kbuild test robot <lkp@intel.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-05-18drm/msm/a6xx: HFI v2 for A640 and A650Jonathan Marek1-6/+111
Add HFI v2 code paths required by Adreno 640 and 650 GPUs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-05-18drm/msm/a6xx: use msm_gem for GMU memory objectsJonathan Marek1-3/+3
This gives more fine-grained control over how memory is allocated over the DMA api. In particular, it allows using an address range or pinning to a fixed address. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-02-11drm/msm/a6xx: Update the GMU bus tables for sc7180Jordan Crouse1-25/+60
Fixup the GMU bus table values for the sc7180 target. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618") Signed-off-by: Rob Clark <robdclark@chromium.org>
2018-12-11drm: msm: Use DRM_DEV_* instead of dev_*Mamta Shukla1-7/+7
Use DRM_DEV_INFO/ERROR/WARN instead of dev_info/err/debug to generate drm-formatted specific log messages so that it will be easy to differentiate in case of multiple instances of driver. Signed-off-by: Mamta Shukla <mamtashukla555@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-04drm/msm/a6xx: Poll for HFI responsesJordan Crouse1-106/+55
The only HFI communication with the GMU on sdm845 happens during initialization and all commands are synchronous. A fancy interrupt tasklet and associated infrastructure is entirely not eeded and puts us at the mercy of the scheduler. Instead poll for the message signal and handle the response immediately and go on our way. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-11drm/msm: Add A6XX device supportJordan Crouse1-0/+435
Add support for the A6XX family of Adreno GPUs. The biggest addition is the GMU (Graphics Management Unit) which takes over most of the power management of the GPU itself but in a ironic twist of fate needs a goodly amount of management itself. Add support for the A6XX core code, the GMU and the HFI (hardware firmware interface) queue that the CPU uses to communicate with the GMU. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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