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path: root/drivers/gpu/drm/i915
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2025-04-24drm/i915/lobf: Add lobf enablement in post plane updateAnimesh Manna4-3/+32
Enablement of LOBF is added in post plane update whenever has_lobf flag is set. As LOBF can be enabled in non-psr case as well so adding in post plane update. There is no change of configuring alpm with psr path. v1: Initial version. v2: Use encoder-mask to find the associated encoder from crtc-state. [Jani] v3: Remove alpm_configure from intel_psr.c. [Jouni] Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-3-animesh.manna@intel.com
2025-04-24drm/i915/alpm: use variable from intel_crtc_state instead of intel_psrJouni Högander1-2/+2
Currently code is making assumption that PSR is enabled when intel_alpm_configure is called. This doesn't work if alpm is configured before PSR is enabled. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-2-animesh.manna@intel.com
2025-04-24drm/i915/reg: Add/remove some extra blank linesJani Nikula1-5/+3
Add/remove some blank lines to/from i915_reg.h primarily to help the scripted refactoring coming up, separating unrelated registers and keeping the comments together. v2: Also add some extra blank lines Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1 Link: https://lore.kernel.org/r/20250423100213.720585-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-24drm/i915/reg: use REG_BIT and friends to define DP registersJani Nikula2-93/+54
Define the DP register contents using the REG_BIT, REG_GENMASK, etc. macros. Ditch the unhelpful comments. Rename eDP related register content macros to have EDP_ prefix. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250423100213.720585-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-23drm/i915/display: Rename vblank DC workaround functions and variablesJouni Högander3-12/+13
We have extended using vblank DC workaround mechanism for Wa_16025596647. Rename related functions and variables: vblank_wa_num_pipes -> vblank_enable_count vblank_dc_work -> vblank_notify_work intel_display_vblank_dc_work -> intel_display_vblank_notify_work Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-14-jouni.hogander@intel.com
2025-04-23drm/i915/display: Rename intel_psr_needs_block_dc_vblankJouni Högander5-9/+11
Scope of intel_psr_needs_block_dc_vblank has changed now. Rename it as intel_psr_needs_vblank_notification. Also rename intel_crtc::block_dc_for_vblank as intel_crtc:vblank_psr_notify Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-13-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Apply underrun on PSR idle workaroundJouni Högander5-48/+61
This patch is applying workaround for underrun on idle PSR HW issue (Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable status, DC5/6 enabled disabled and enabled pipes count information made available. This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe enable/disable notification functions as needed. intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable notification on PSR capable system. v2: use intel_dmc interface instead of directly writing dmc register Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-12-jouni.hogander@intel.com
2025-04-23drm/i915/dmc: Add interface to control start of PKG C-state exitJouni Högander2-0/+33
Add interface to control if package C exit starts at the start of the undelayed vblank. This is needed to implement workaround for underrun on idle PSR HW issue (Wa_16025596647). Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-11-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Add interface to notify PSR of vblank enable/disableJouni Högander2-0/+42
To implement Wa_16025596647 we need to get notification of vblank interrupt enable/disable. Add new interface to PSR code for this notification. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-10-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disableJouni Högander3-0/+54
We need to apply/remove workaround for underrun on idle PSR HW issue (Wa_16025596647) when DC5/6 is enabled/disabled. This patch implements mechanism to notify PSR about DC5/6 enable/disable and applies/removes the workaround using this notification. Bspec: 74115 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-9-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Add mechanism to notify PSR of pipe enable/disableJouni Högander2-0/+108
We need to apply/remove workaround for underrun on idle PSR HW issue (Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This patch implements mechanism to notify PSR about pipe enable/disable and applies/removes the workaround using this notification. Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-8-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Block PKG C-State when enabling PSRJouni Högander1-0/+13
Block PKG C-State when enabling PSR when enabling PSR as described in workaround for underrun on idle PSR HW issue (Wa_16025596647). v2: use intel_dmc_block_pkgc instead of directly writing dmc register Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-7-jouni.hogander@intel.com
2025-04-23drm/i915/dmc: Add interface to block PKG C-stateJouni Högander2-0/+19
Add interface to block PKG C-state. This is needed to implement workaround for underrun on idle PSR HW issue (Wa_16025596647). Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-6-jouni.hogander@intel.com
2025-04-23drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitionsJouni Högander1-0/+8
We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW register definitions. Bspec: 71265 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-5-jouni.hogander@intel.com
2025-04-23drm/i915/dmc: Add PIPEDMC_EVT_CTL register definitionJouni Högander1-0/+6
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register definitions. Bspec: 67576 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-4-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Store enabled non-psr pipes into intel_crtc_stateJouni Högander2-0/+26
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) we need to know enabled. Figure out which non-PSR pipes we will have active and store it into intel_crtc_state->active_non_psr_pipes. This is currently assuming only one eDP on a time. I.e. possible secondary eDP with PSR capable panel is not considered. Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-3-jouni.hogander@intel.com
2025-04-23drm/i915/display: Add new interface for getting dc_stateJouni Högander2-0/+30
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) we need to have current configured DC state available. Add new interface for this purpose. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-2-jouni.hogander@intel.com
2025-04-22drm/i915/pch: abstract fake PCH detection betterJani Nikula1-19/+28
Abstract detection of platforms with south display on the same PCI device or SoC die as north display, and all around clarify what this means. Debug log about it for good measure. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/95cd619b63a81a0a7f8c73a64694da9d41e3a575.1744880985.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-22drm/i915/display: drop lots of unnecessary #include i915_drv.hJani Nikula23-26/+57
With the PCH macros switched to use struct intel_display, we have a number of files that no longer need struct drm_i915_private or anything else from i915_drv.h anymore. Remove the #include, and add the missing includes that were previously implicit. v2: Drop even more of the includes Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/5dc9e6a98461c344febac4c645875d8688eba906.1744880985.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-22drm/i915/display: pass struct intel_display to PCH macrosJani Nikula28-336/+201
Now that INTEL_PCH_TYPE() and HAS_PCH_*() macros are under display, and accept a struct intel_display pointer, use that instead of struct drm_i915_private pointer in display code. This is done naively by running: $ sed -i 's/\(INTEL_PCH_TYPE\|HAS_PCH_[A-Z0-9_-]*\)([^)]*)/\1(display)/g' \ $(find drivers/gpu/drm/i915/display -name "*.c") and fixing the fallout, i.e. removing unused local i915 variables and adding display variables where needed. v2: Rebase Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/999f4d7b8ed11739b1c5ec8d6408fc39d5e3776b.1744880985.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-22drm/i915/pxp: fix undefined reference to `intel_pxp_gsccs_is_ready_for_sessions'Chen Linxuan1-2/+6
On x86_64 with gcc version 13.3.0, I compile kernel with: make defconfig ./scripts/kconfig/merge_config.sh .config <( echo CONFIG_COMPILE_TEST=y ) make KCFLAGS="-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once" Then I get a linker error: ld: vmlinux.o: in function `pxp_fw_dependencies_completed': kintel_pxp.c:(.text+0x95728f): undefined reference to `intel_pxp_gsccs_is_ready_for_sessions' This is caused by not having a intel_pxp_gsccs_is_ready_for_sessions() header stub for CONFIG_DRM_I915_PXP=n. Add it. Signed-off-by: Chen Linxuan <chenlinxuan@uniontech.com> Fixes: 99afb7cc8c44 ("drm/i915/pxp: Add ARB session creation and cleanup") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250415090616.2649889-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit b484c1e225a6a582fc78c4d7af7b286408bb7d41) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/audio: don't set LPE audio irq chip data, it's unusedJani Nikula1-1/+1
Nobody uses the irq chip data. Stop setting it, and as a bonus get rid of another struct drm_i915_private * reference. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/d75ec986093c912de67a42782aa5a49357a9f8e5.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/display: switch to display->platform.dgfx from IS_DGFX()Jani Nikula3-6/+8
Prefer display->platform.dgfx based platform detection over the old IS_DGFX() macro. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/99de7f8f26156afbddcdac850088e6a96d322c55.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/hdmi: switch to display->platform based platform detectionJani Nikula1-24/+20
Prefer display->platform based platform detection over the old IS_*() macros. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/02659f1144180f328167734f7e31499833749c8d.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/gmbus: switch to display->platform based platform detectionJani Nikula1-13/+9
Prefer display->platform based platform detection over the old IS_*() macros. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/7a69d2ffa15306da899b98e0d6af09b4df1b7ec3.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/dpio: switch to display->platform based platform detectionJani Nikula1-3/+1
Prefer display->platform based platform detection over the old IS_*() macros. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/36166cd0cfdb88df4c0322c4edea69fad5ad7177.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/dp-aux: switch to display->platform based platform detectionJani Nikula1-5/+4
Prefer display->platform based platform detection over the old IS_*() macros. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/a5cde717001eb2843344beb21ca8907ab2e43d4f.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/dmc: switch to display->platform based platform detectionJani Nikula1-26/+19
Prefer display->platform based platform detection over the old IS_*() macros. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/eda2b6cd285ec76d57d91ea3fe33158852aaec22.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/crt: switch to display->platform based platform detectionJani Nikula1-7/+6
Prefer display->platform based platform detection over the old IS_*() macros. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/83980c1ae53157ef5d65d7ce99b294889622faa8.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/frontbuffer: convert intel_frontbuffer.[ch] to struct intel_displayJani Nikula4-44/+37
Going forward, struct intel_display is the main display device data pointer. Convert intel_frontbuffer.[ch] to struct intel_display. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/ef0860583b7d6ad141959f84c25657e0c102d6d2.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/sprite: convert intel_sprite_uapi.c to struct intel_displayJani Nikula1-9/+8
Going forward, struct intel_display is the main display device data pointer. Convert intel_sprite_uapi.c to struct intel_display. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/d4f71c2976a1a28b4e74c2fc1097090fe7f78743.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/display: convert intel_modeset_verify.c to struct intel_displayJani Nikula1-10/+7
Going forward, struct intel_display is the main display device data pointer. Convert intel_modeset_verify.[ch] to struct intel_display. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/b01a3ef3dbb2ffdaa6b5e9ebec14f91efcca3049.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/display: convert intel_modeset_setup.[ch] to struct intel_displayJani Nikula3-105/+97
Going forward, struct intel_display is the main display device data pointer. Convert intel_modeset_setup.[ch] to struct intel_display. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/21d51387a36f027313a0687d09a14586eb8f71a6.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-17drm/i915/fb: convert intel_fbdev.[ch] and intel_fbdev_fb.[ch] to struct ↵Jani Nikula5-52/+48
intel_display Going forward, struct intel_display is the main display device data pointer. Convert intel_fbdev.[ch] and as much as possible of intel_fbdev_fb.[ch] to struct intel_display. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/49651754f3716041f97984e47c15d331851870a5.1744222449.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-16drm/i915/pxp: fix undefined reference to `intel_pxp_gsccs_is_ready_for_sessions'Chen Linxuan1-2/+6
On x86_64 with gcc version 13.3.0, I compile kernel with: make defconfig ./scripts/kconfig/merge_config.sh .config <( echo CONFIG_COMPILE_TEST=y ) make KCFLAGS="-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once" Then I get a linker error: ld: vmlinux.o: in function `pxp_fw_dependencies_completed': kintel_pxp.c:(.text+0x95728f): undefined reference to `intel_pxp_gsccs_is_ready_for_sessions' This is caused by not having a intel_pxp_gsccs_is_ready_for_sessions() header stub for CONFIG_DRM_I915_PXP=n. Add it. Signed-off-by: Chen Linxuan <chenlinxuan@uniontech.com> Fixes: 99afb7cc8c44 ("drm/i915/pxp: Add ARB session creation and cleanup") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250415090616.2649889-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-15drm/i915/irq: convert ibx_irq_reset() into ibx_display_irq_reset()Jani Nikula3-20/+20
Observe that ibx_irq_reset() is really ibx_display_irq_reset(). Make it so. Move to display, and call it directly from gen8_display_irq_reset() instead of gen8_irq_reset(). Remove a nearby ancient stale comment while at it. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/20250409184702.3790548-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-15Merge drm/drm-next into drm-misc-nextThomas Zimmermann127-4659/+5402
Backmerging to get fixes from v6.15-rc2 into drm-misc-next. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2025-04-15drm/i915/display: Add link rate and lane count to i915_display_infoKhaled Almahallawy1-0/+2
Adding link rate and lane count information to i915_display_info makes it easier and faster to access this data compared to checking kernel logs. This is particularly beneficial for individuals who are not familiar with i915 in the following scenarios: * Debugging DP tunnel bandwidth usage in the Thunderbolt driver. * During USB4 certification, it is necessary to know the link rate used by the monitor to prove that the DP tunnel can handle required rates. * In PHY CTS, when the connector probes are not mounted correctly, some display lanes may not appear in the DP Oscilloscope, leading to CTS failures. This change provides validation teams with an easy way to identify and troubleshoot issues. v2: separate seq_printf line (Jani) v3: separate output line (Jani) Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250409230214.963999-1-khaled.almahallawy@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-15drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slicesAnkit Nautiyal1-3/+4
DSC 12 slices configuration is used for some specific cases with Ultrajoiner. This can be supported only when each of the 4 joined pipes have 3 DSC engines each. Add the missing check for 3 DSC engines support before using 3 DSC slices per pipe. Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: <stable@vger.kernel.org> # v6.14+ Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250414024256.2782702-3-ankit.k.nautiyal@intel.com (cherry picked from commit da9b1c61e7f7b327dd70c5f073ba04d419a55ef8) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-15drm/i915/display: Add macro for checking 3 DSC enginesAnkit Nautiyal1-0/+1
3 DSC engines per pipe is currently supported only for BMG. Add a macro to check whether a platform supports 3 DSC engines per pipe. v2:Fix Typo in macro argument. (Suraj). Added fixes tag. Bspec: 50175 Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: <stable@vger.kernel.org> # v6.14+ Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250414085701.2802374-1-ankit.k.nautiyal@intel.com (cherry picked from commit 6998cfce0e1db58c730d08cadc6bfd71e26e2de0) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-15drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slicesAnkit Nautiyal1-3/+4
DSC 12 slices configuration is used for some specific cases with Ultrajoiner. This can be supported only when each of the 4 joined pipes have 3 DSC engines each. Add the missing check for 3 DSC engines support before using 3 DSC slices per pipe. Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: <stable@vger.kernel.org> # v6.14+ Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250414024256.2782702-3-ankit.k.nautiyal@intel.com
2025-04-15drm/i915/display: Add macro for checking 3 DSC enginesAnkit Nautiyal1-0/+1
3 DSC engines per pipe is currently supported only for BMG. Add a macro to check whether a platform supports 3 DSC engines per pipe. v2:Fix Typo in macro argument. (Suraj). Added fixes tag. Bspec: 50175 Fixes: be7f5fcdf4a0 ("drm/i915/dp: Enable 3 DSC engines for 12 slices") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: <stable@vger.kernel.org> # v6.14+ Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250414085701.2802374-1-ankit.k.nautiyal@intel.com
2025-04-14Merge tag 'drm-intel-next-2025-04-11' of ↵Dave Airlie121-4630/+5308
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Cross-subsystem Changes: - Update GVT MAINTAINERS (Jani) Driver Changes: - Updates for xe3lpd display (Gustavo) - Fix link training interrupted by HPD pulse (Imre) - Watermark bound checks for DSC (Ankit) - VRR Refactor and other fixes and improvements (Ankit) - More conversions towards intel_display struct (Gustavo, Jani) - Other clean-up patches towards a display separation (Jani) - Maintain asciibetical order for HAS_* macros (Ankit) - Fixes around probe/initialization (Janusz) - Fix build and doc build issue (Yue, Rodrigo) - DSI related fixes (Suraj, William, Jani) - Improve DC6 entry counter (Mohammed) - Fix xe2hpd memory type identification (Vivek) - PSR related fixes and improvements (Animesh, Jouni) - DP MST related fixes and improvements (Imre) - Fix scanline_offset for LNL+/BMG+ (Ville) - Some gvt related fixes and changes (Ville, Jani) - Some PLL code adjustment (Ville) - Display wa addition (Vinod) - DRAM type logging (Lucas) - Pimp the initial FB readout (Ville) - Some sagv/bw cleanup (Ville) - Remove i915_display_capabilities debugfs entry (Jani) - Move PCH type to display caps debugfs entry (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/Z_kTqPX5Mjruq1pL@intel.com
2025-04-14drm/i915: use graphics version instead of PCH split in error captureJani Nikula1-1/+1
Avoid using PCH checks in core i915 code, in preparation for moving PCH handling to display. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/8d73eb1d56603210003554bc6a875c53ed4c692a.1744630147.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-14drm/i915: don't capture DERRMR for VLV/CHVJani Nikula1-1/+1
DERRMR isn't valid for VLV/CHV. Don't capture it for them. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/4563cc7eb567ac508b84717c3708a4e48aa8b7bb.1744630147.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-14drm/i915: use display snapshot mechanism for display irq regsJani Nikula5-20/+38
Move more display specific parts of GPU error logging behind the display snapshot interface. With the display register capture reduced to just one register, DERRMR, there's quite a bit of boilerplate here. However, it's still a nice abstraction and removes a DISPLAY_VER() usage from core i915. With this approach, it's also easy to add to xe as needed. v2: Remove stale comment Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/13206969df04426d290d2863dc574e22ca45193a.1744630147.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-14drm/i915: stop recording IER in error captureJani Nikula2-9/+0
With pre-ilk GEN2_IER capture moved to gtier[0], the remaining IER aren't all that relevant. Stop capturing them. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/6f1130a3d0d13e08a73ba381225ab978b22a9345.1744630147.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-14drm/i915: record GEN2_IER in gtier[0] for pre-ilk error captureJani Nikula1-2/+3
In pre-ilk platforms the engine interrupts live in GEN2_IER. Capture it as part of gtier instead of display. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/f637219fe3accb69963266773b9ef7c1131875e4.1744630147.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-14drm/i915: use 32-bit access for gen2 irq registersJani Nikula1-2/+0
We've previously switched from 16-bit to 32-bit access for gen2 irq registers, but one was left behind. Fix it. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/5a56286c94e08a02435c60ce0fbff13aca6c0d1f.1744630147.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-14drm/i915/dpio: have chv_data_lane_soft_reset() get/put dpio internallyJani Nikula3-20/+16
Have chv_data_lane_soft_reset() get/put dpio internally, and use a locked version of it within intel_dpio_phy.c. This drops the dependency on vlv sideband from g4x_dp.c and g4x_hdmi.c, and makes that a DPIO PHY implementation detail. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/20250411102715.613082-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-11 13:55:18 +0300