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2021-05-20drm/i915/display: Add PSR interrupt error check functionGwan-gyeong Mun1-18/+29
In order to reuse code of PSR interrupt error check on other PSR functions, it adds psr_interrupt_error_check() function. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-13-lucas.demarchi@intel.com
2021-05-20drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr structGwan-gyeong Mun2-6/+6
It replaces dc3co_enabled with dc3co_exitline on intel_psr struct. And it saves dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline without intel_crtc_state on other psr internal function like as intel_psr_enable_source(). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-12-lucas.demarchi@intel.com
2021-05-20drm/i915/adl_p: Tx escape clock with DSIMika Kahola2-2/+25
Today when the DSI controller is paired with the Combo-PHY it uses the high-speed (HS) Word clock for its low power (LP) transmit PPI communication to the DPHY. The interface signaling only changes state at an Escape clock frequency (i.e. its effectively running on a virtual Tx Escape clock that is controlled by counters w/in the controller), but all the interface flops are running off the HS clock. This has the following drawbacks: * It is a deviation from the PPI spec which assumes signaling is running on a physical Escape clock * The PV timings are over constrained (HS timed to 312.5MHz vs. an Escape clock of 20MHz max) This feature is proposing to change the LP Tx communication between the controller and the DPHY from a virtual Tx Escape clock to a physical clock. To do this we need to program two "M" divisors. One for the usual DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV register and one for MIPIO_DWORD8. For DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV registers the "M" is calculated as following Nt = ceil(f_link/160) (theoretical word clock) Nact = max[3, Nt + (Nt + 1)%2] (actual word clock) M = Nact * 8 For MIPIO_DWORD8 register, the divisor "M" is calculated as following M = (Nact - 1)/2 BSpec: 55171 Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-11-lucas.demarchi@intel.com
2021-05-20drm/i915/adl_p: MBUS programmingVandita Kulkarni6-9/+120
Update MBUS_CTL register if the 2 mbus can be joined as per the current DDB allocation and active pipes, also update hashing mode and pipe select bits as per the sequence mentioned in the bspec. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-10-lucas.demarchi@intel.com
2021-05-20drm/i915: Introduce MBUS relative dbuf offsetsVille Syrjälä1-6/+34
The dbuf slices are going to be split across several MBUS units. The actual dbuf programming will use offsets relative to the MBUS unit. To accommodate that we shall store the MBUS relative offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[]. For crtc_state->wm.skl.ddb however we want to stick to global offsets as we use this to sanity check that the ddb allocations don't overlap between pipes. Cc: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-9-lucas.demarchi@intel.com
2021-05-20drm/i915/adl_p: Add ddb allocation supportVandita Kulkarni2-5/+138
On adlp the two mbuses have two display pipes and two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on Mbus2. The Mbus can be joined and all the DBUFS can be used on Pipe A or B. Bspec: 49255 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-8-lucas.demarchi@intel.com
2021-05-20drm/i915/adl_p: Don't config MBUS and DBUF during display initializationJosé Roberto de Souza1-0/+6
Alderlake-P don't have programing sequences for MBUS or DBUF during display initializaiton, instead it requires programing to those registers during modeset because it to depend on the pipes left enabled. Bspec: 49213 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-7-lucas.demarchi@intel.com
2021-05-20drm/i915/adl_p: Implement TC sequencesJosé Roberto de Souza3-11/+137
ADL-P have basically the same TC connection and disconnection sequences as ICL and TGL, the major difference is the new registers. So here adding functions without the icl prefix in the name and making the new functions call the platform specific function to access the correct register. v2: - Retain DDI TC PHY ownership flag during modesetting. BSpec: 55480 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-6-lucas.demarchi@intel.com
2021-05-20drm/i915/adl_p: Setup ports/physAnusha Srivatsa1-2/+11
The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4. The first two are connected to combo phys while the rest are connected to TC phys. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-5-lucas.demarchi@intel.com
2021-05-20drm/i915/adl_p: Add dedicated SAGV watermarksMatt Roper4-21/+126
XE_LPD reduces the number of regular watermark latency levels from 8 to 6 on non-dgfx platforms. However the hardware also adds a special purpose SAGV wateramrk (and an accompanying transition watermark) that will be used by the hardware in place of the level 0 values during SAGV transitions. Bspec: 49325, 49326, 50419 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-4-lucas.demarchi@intel.com
2021-05-20drm/i915/xelpd: Add rc_qp_table for rcparams calculationVandita Kulkarni4-1/+333
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by the VESA C model for DSC 1.1 v2: - Add include guard to header (Jani) - Move the big tables to a .c file (Chris, Jani, Lucas) v3: - Make tables 'static const' and add lookup functions to index into them. (Jani) v3.1: - Include missing .h file. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-3-lucas.demarchi@intel.com
2021-05-20drm/i915/xelpd: Calculate VDSC RC parametersVandita Kulkarni1-10/+87
Add methods to calculate rc parameters for all bpps, against the fixed arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444 formats. Our hw doesn't support YUV compression yet. The calculations used here are from VESA C model for DSC 1.1 v2: - Checkpatch fixes Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Juha-Pekka Heikkil <juha-pekka.heikkila@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Mohammed Khajapasha <mohammed.khajapasha@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-2-lucas.demarchi@intel.com
2021-05-20Merge tag 'drm-misc-next-2021-05-17' of ↵Dave Airlie1-4/+2
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.14: UAPI Changes: Cross-subsystem Changes: Core Changes: * aperture: Fix unlocking on errors * legacy: Fix some doc comments Driver Changes: * drm/amdgpu: Free resource on fence usage query; Fix fence calculation; * drm/bridge: Lt9611: Add missing MODULE_DEVICE_TABLE * drm/i915: Print formats with %p4cc * drm/ingenic: IPU planes are now always of type OVERLAY * drm/nouveau: Remove left-over reference to struct drm_device.pdev * drm/panfrost: Disable devfreq if num_supplies > 1; Add Mediatek MT8183 + DT bindings; Cleanups * drm/simpledrm: Print resources with %pr; Fix use-after-free errors; Fix NULL deref; Fix MAINTAINERS entry * drm/vmwgfx: Fix memory allocation and leak in FIFO allocation; Fix return value in PCI resource setup Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/YKJs2IfwSYvuGPU7@linux-uq9g.fritz.box
2021-05-20drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.hAnusha Srivatsa8-11/+11
Finally, rename the header and source file from csr to dmc. v2: Add file rename in Documentation. - Place headers in orders. (Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210518213444.11420-6-anusha.srivatsa@intel.com
2021-05-20drm/i915/dmc: Rename functions names having "csr"Anusha Srivatsa5-54/+54
No functional change. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210518213444.11420-5-anusha.srivatsa@intel.com
2021-05-20drm/i915/dmc: Rename macro names containing csrAnusha Srivatsa6-118/+117
Rename all occurences of CSR_* with DMC_* Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210518213444.11420-4-anusha.srivatsa@intel.com
2021-05-20drm/i915/dmc: s/HAS_CSR/HAS_DMCAnusha Srivatsa7-13/+13
No functional change. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210518213444.11420-3-anusha.srivatsa@intel.com
2021-05-20drm/i915/dmc: s/intel_csr/intel_dmcAnusha Srivatsa6-125/+125
No functional change. v2: Chchpatch fixes. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210518213444.11420-2-anusha.srivatsa@intel.com
2021-05-19gpu: drm: replace occurrences of invalid characterMauro Carvalho Chehab2-2/+2
There are some places at drm that ended receiving a REPLACEMENT CHARACTER U+fffd ('�'), probably because of some bad charset conversion. Fix them by using what it seems to be the proper character. Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/e606930c73029f16673849c57acac061dd923866.1621412009.git.mchehab+huawei@kernel.org
2021-05-19Revert "i915: fix remap_io_sg to verify the pgprot"Linus Torvalds1-23/+50
This reverts commit b12d691ea5e01db42ccf3b4207e57cb3ce7cfe91. It turns out this is not ready for primetime yet. The intentions are good, but using remap_pfn_range() requires that there is nothing already mapped in the area, and the i915 code seems to very much intentionally remap the same area multiple times. That will then just trigger the BUG_ON(!pte_none(*pte)); in mm/memory.c: remap_pte_range(). There are also reports of mapping type inconsistencies, resulting in warnings and in screen corruption. Link: https://lore.kernel.org/lkml/20210519024322.GA29704@xsang-OptiPlex-9020/ Link: https://lore.kernel.org/lkml/YKUjvoaKKggAmpIR@sf/ Link: https://lore.kernel.org/lkml/b6b61cf0-5874-f4c0-1fcc-4b3848451c31@redhat.com/ Reported-by: kernel test robot <oliver.sang@intel.com> Reported-by: Kalle Valo <kvalo@codeaurora.org> Reported-by: Hans de Goede <hdegoede@redhat.com> Reported-by: Sergei Trofimovich <slyfox@gentoo.org> Acked-by: Christoph Hellwig <hch@lst.de> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2021-05-19Merge tag 'gvt-fixes-2021-05-19' of https://github.com/intel/gvt-linux into ↵Jani Nikula6-138/+118
drm-intel-fixes gvt-fixes-2021-05-19 - Fix workaround in -rc1 for GVT config (Zhenyu) Signed-off-by: Jani Nikula <jani.nikula@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519074912.GG4589@zhen-hp.sh.intel.com
2021-05-19drm/i915/gt: Disable HiZ Raw Stall Optimization on broken gen7Simon Rettberg1-1/+4
When resetting CACHE_MODE registers, don't enable HiZ Raw Stall Optimization on Ivybridge GT1 and Baytrail, as it causes severe glitches when rendering any kind of 3D accelerated content. This optimization is disabled on these platforms by default according to official documentation from 01.org. Fixes: ef99a60ffd9b ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals") BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3081 BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3404 BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3071 Reviewed-by: Manuel Bentele <development@manuel-bentele.de> Signed-off-by: Simon Rettberg <simon.rettberg@rz.uni-freiburg.de> Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Rodrigo removed invalid Fixes line] Link: https://patchwork.freedesktop.org/patch/msgid/20210426161124.2b7fd708@dellnichtsogutkiste (cherry picked from commit 929b734ad34b717d6a1b8de97f53bb5616040147) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2021-05-19drm/i915/gem: Pin the L-shape quirked object as unshrinkableChris Wilson2-6/+7
When instantiating a tiled object on an L-shaped memory machine, we mark the object as unshrinkable to prevent the shrinker from trying to swap out the pages. We have to do this as we do not know the swizzling on the individual pages, and so the data will be scrambled across swap out/in. Not only do we need to move the object off the shrinker list, we need to mark the object with shrink_pin so that the counter is consistent across calls to madvise. v2: in the madvise ioctl we need to check if the object is currently shrinkable/purgeable, not if the object type supports shrinking Fixes: 0175969e489a ("drm/i915/gem: Use shrinkable status for unknown swizzle quirks") References: https://gitlab.freedesktop.org/drm/intel/-/issues/3293 References: https://gitlab.freedesktop.org/drm/intel/-/issues/3450 Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: <stable@vger.kernel.org> # v5.12+ Link: https://patchwork.freedesktop.org/patch/msgid/20210517084640.18862-1-matthew.auld@intel.com (cherry picked from commit 8777d17b68dcfbfbd4d524f444adefae56f41225) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2021-05-19Merge tag 'drm-misc-next-2021-05-12' of ↵Dave Airlie12-41/+33
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.14: UAPI Changes: * drm: Disable connector force-probing for non-master clients * drm: Enforce consistency between IN_FORMATS property and cap + related driver cleanups * drm/amdgpu: Track devices, process info and fence info via /proc/<pid>/fdinfo * drm/ioctl: Mark AGP-related ioctls as legacy * drm/ttm: Provide tt_shrink file to trigger shrinker via debugfs; Cross-subsystem Changes: * fbdev/efifb: Special handling of non-PCI devices * fbdev/imxfb: Fix error message Core Changes: * drm: Add connector helper to attach HDR-metadata property and convert drivers * drm: Add connector helper to compare HDR-metadata and convert drivers * drm: Add conenctor helper to attach colorspace property * drm: Signal colorimetry in HDMI infoframe * drm: Support pitch for destination buffers; Add blitter function with generic format conversion * drm: Remove struct drm_device.pdev and update legacy drivers * drm: Remove obsolete DRM_KMS_FB_HELPER config option in core and drivers * drm: Remove obsolete drm_pci_alloc/drm_pci_free * drm/aperture: Add helpers for aperture ownership and convert drivers, replaces rsp fbdev helpers * drm/agp: Mark DRM AGP code as legacy and convert legacy drivers * drm/atomic-helpers: Cleanups * drm/dp: Handle downstream port counts of 0 correctly; AUX channel fixes; Use drm_err_*/drm_dbg_*(); Cleanups * drm/dp_dual_mode: Use drm_err_*/drm_dbg_*() * drm/dp_mst: Use drm_err_*/drm_dbg_*(); Use Extended Base Receiver Capability DPCD space * drm/gem-ttm-helper: Provide helper for dumb_map_offset and convert drivers * drm/panel: Use sysfs_emit; panel-simple: Use runtime PM, Power up panel when reading EDID, Cache EDID, Cleanups; Lms397KF04: DT bindings * drm/pci: Mark AGP helpers as legacy * drm/print: Handle NULL for DRM devices gracefully * drm/scheduler: Change scheduled fence track * drm/ttm: Don't count SG BOs against pages_limit; Warn about freeing pinned BOs; Fix error handling if no BO can be swapped out; Move special handling of non-GEM drivers into vmwgfx; Move page_alignment into the BO; Set drm-misc as TTM tree in MAINTAINERS; Cleanup ttm_agp_backend; Add ttm_sys_manager for system domain; Cleanups Driver Changes: * drm: Don't set allow_fb_modifiers explictly in drivers * drm/amdgpu: Pin/unpin fixes wrt to TTM; Use bo->base.size instead of mem->num_pages * drm/ast: Use managed pcim_iomap(); Fix EDID retrieval with DP501 * drm/bridge: MHDP8546: HDCP support + DT bindings, Register DP AUX channel with userspace; Sil8620: Fix module dependencies; dw-hdmi: Add option to not load CEC driver; Fix stopping in drm_bridge_chain_pre_enable(); Ti-sn65dsi86: Fix refclk handling, Break GPIO and MIPI-to-eDP into subdrivers, Use pm_runtime autosuspend, cleanups; It66121: Add driver + DT bindings; Adv7511: Support I2S IEC958 encoding; Anx7625: fix power-on delay; Nwi-dsi: Modesetting fixes; Cleanups * drm/bochs: Support screen blanking * drm/gma500: Cleanups * drm/gud: Cleanups * drm/i915: Use correct max source link rate for MST * drm/kmb: Cleanups * drm/meson: Disable dw-hdmi CEC driver * drm/nouveau: Pin/unpin fixes wrt to TTM; Use bo->base.size instead of mem->num_pages; Register AUX adapters after their connectors * drm/qxl: Fix shadow BO unpin * drm/radeon: Duplicate some DRM AGP code to uncouple from legacy drivers * drm/simpledrm: Add a generic DRM driver for simple-framebuffer devices * drm/tiny: Fix log spam if probe function gets deferred * drm/vc4: Add support for HDR-metadata property; Cleanups * drm/virtio: Create dumb BOs as guest blobs; * drm/vkms: Use managed drmm_universal_plane_alloc(); Add XRGB plane composition; Add overlay support * drm/vmwgfx: Enable console with DRM_FBDEV_EMULATION; Fix CPU updates of coherent multisample surfaces; Remove reservation semaphore; Add initial SVGA3 support; Support amd64; Use 1-based IDR; Use min_t(); Cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/YJvkD523evviED01@linux-uq9g.fritz.box
2021-05-18drm/i915: Initialize err in remap_io_sg()José Roberto de Souza1-1/+1
If the do while loop breaks in 'if (!sg_dma_len(sgl))' in the first iteration, err is uninitialized causing a wrong call to zap_vma_ptes(). But that is impossible to happen as a scatterlist must have at least one valid segment. Anyways to avoid more reports from static checkers initializing ret here. Fixes: b12d691ea5e0 ("i915: fix remap_io_sg to verify the pgprot") Reviewed-by: Christoph Hellwig <hch@lst.de> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210517202117.179303-1-jose.souza@intel.com
2021-05-18drm/i915/gt: Disable HiZ Raw Stall Optimization on broken gen7Simon Rettberg1-1/+4
When resetting CACHE_MODE registers, don't enable HiZ Raw Stall Optimization on Ivybridge GT1 and Baytrail, as it causes severe glitches when rendering any kind of 3D accelerated content. This optimization is disabled on these platforms by default according to official documentation from 01.org. Fixes: ef99a60ffd9b ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals") BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3081 BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3404 BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3071 Reviewed-By: Manuel Bentele <development@manuel-bentele.de> Signed-off-by: Simon Rettberg <simon.rettberg@rz.uni-freiburg.de> Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Rodrigo removed invalid Fixes line] Link: https://patchwork.freedesktop.org/patch/msgid/20210426161124.2b7fd708@dellnichtsogutkiste
2021-05-18Merge drm/drm-next into drm-intel-nextRodrigo Vivi19-165/+93
Time to get back in sync... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2021-05-17drm/i915: Don't include drm_legacy.hThomas Zimmermann2-2/+0
i915 does not use DRM legacy code. Remove the rsp include statements. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210516185937.5644-2-tzimmermann@suse.de
2021-05-17drm/i915/gem: Pin the L-shape quirked object as unshrinkableChris Wilson2-6/+7
When instantiating a tiled object on an L-shaped memory machine, we mark the object as unshrinkable to prevent the shrinker from trying to swap out the pages. We have to do this as we do not know the swizzling on the individual pages, and so the data will be scrambled across swap out/in. Not only do we need to move the object off the shrinker list, we need to mark the object with shrink_pin so that the counter is consistent across calls to madvise. v2: in the madvise ioctl we need to check if the object is currently shrinkable/purgeable, not if the object type supports shrinking Fixes: 0175969e489a ("drm/i915/gem: Use shrinkable status for unknown swizzle quirks") References: https://gitlab.freedesktop.org/drm/intel/-/issues/3293 References: https://gitlab.freedesktop.org/drm/intel/-/issues/3450 Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: <stable@vger.kernel.org> # v5.12+ Link: https://patchwork.freedesktop.org/patch/msgid/20210517084640.18862-1-matthew.auld@intel.com
2021-05-17drm/i915/gvt: Move mdev attribute groups into kvmgt moduleZhenyu Wang6-138/+118
As kvmgt module contains all handling for VFIO/mdev, leaving mdev attribute groups in gvt module caused dependency issue. Although it was there for possible other hypervisor usage, that turns out never to be true. So this moves all mdev handling into kvmgt module completely to resolve dependency issue. With this fix, no config workaround is required. So revert previous workaround commits: adaeb718d46f ("vfio/gvt: fix DRM_I915_GVT dependency on VFIO_MDEV") and 07e543f4f9d1 ("vfio/gvt: Make DRM_I915_GVT depend on VFIO_MDEV"). Reviewed-by: Colin Xu <colin.xu@intel.com> Cc: Arnd Bergmann <arnd@kernel.org> Cc: Jason Gunthorpe <jgg@ziepe.ca> Cc: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20210513083902.2822350-1-zhenyuw@linux.intel.com
2021-05-15drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057)José Roberto de Souza1-1/+19
Buffer compression is not usable in A stepping. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton A Taylor <clinton.a.taylor@intel.com> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-20-matthew.d.roper@intel.com
2021-05-15drm/i915/display/adl_p: Implement Wa_22011320316José Roberto de Souza1-1/+20
Implementation details are in the HSD 22011320316, requiring CD clock to be at least 307MHz to make DC states to work. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-19-matthew.d.roper@intel.com
2021-05-15drm/i915/adl_p: Implement Wa_22011091694José Roberto de Souza2-1/+14
Adding a new hook to ADL-P just to avoid another platform check in gen12lp_init_clock_gating() but also open to it. BSpec: 54369 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-18-matthew.d.roper@intel.com
2021-05-15drm/i915/adl_p: Add IPs stepping mappingJosé Roberto de Souza2-1/+19
This will allow us to better implement workarounds. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-17-matthew.d.roper@intel.com
2021-05-15drm/i915/bigjoiner: atomic commit changes for uncompressed joinerAnimesh Manna4-1/+49
Respective bit for master or slave to be set for uncompressed bigjoiner in dss_ctl1 register. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-16-matthew.d.roper@intel.com
2021-05-15drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoinerAnimesh Manna1-2/+6
For uncompressed big joiner DSC engine will not be used so will avoid compute config of DSC. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-15-matthew.d.roper@intel.com
2021-05-15drm/i915/bigjoiner: Mode validation with uncompressed pipe joinerAnimesh Manna1-2/+5
No need for checking dsc flag for uncompressed pipe joiner mode validation. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-14-matthew.d.roper@intel.com
2021-05-15drm/i915/adl_p: Enable/disable loadgen sharingMika Kahola2-0/+9
Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz. For all other modes, we can enable loadgen sharing feature. BSpec: 55359 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-13-matthew.d.roper@intel.com
2021-05-15drm/i915: Move intel_modeset_all_pipes()Ville Syrjälä3-38/+39
Move intel_modeset_all_pipes() to a central place so that we can use it elsewhere as well. No functional changes. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-12-matthew.d.roper@intel.com
2021-05-15drm/i915/adl_p: Enable modular fiaJosé Roberto de Souza2-0/+5
Alderlake P have modular FIA like TGL but it is always modular in all skus, not like TGL that we had to read a register to check if it is monolithic or modular. BSpec: 55480 BSpec: 50572 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-11-matthew.d.roper@intel.com
2021-05-15drm/i915/display/tc: Rename safe_mode functions ownershipJosé Roberto de Souza1-18/+17
When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display has the control over the TC phy. The "not safe" naming is confusing using ownership make it easier to read also future platforms will have a new register that does the same job as DP_PHY_MODE_STATUS_NOT_SAFE but with the onwership name. BSpec: 49294 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-10-matthew.d.roper@intel.com
2021-05-15drm/i915/adl_p: Add cdclk support for ADL-PAnusha Srivatsa1-13/+28
ADL-P has 3 possible refclk frequencies: 19.2MHz, 24MHz and 38.4MHz While we're at it, remove the drm_WARNs. They've never actually helped us catch any problems, but it's very easy to forget to update them properly for new platforms. BSpec: 55409, 49208 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-9-matthew.d.roper@intel.com
2021-05-15drm/i915/adl_p: Extend PLANE_WM bits for blocks & linesMatt Roper1-2/+2
ADL-P further extends the bits in PLANE_WM that represent blocks and lines; we need to extend our masks accordingly. Since these bits are reserved and MBZ on earlier platforms, it's safe to use the larger bitmask on all platforms. Bspec: 50419 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-8-matthew.d.roper@intel.com
2021-05-15drm/i915/xelpd: Provide port/phy mapping for vbtJosé Roberto de Souza1-1/+17
This will allow proper DDI initialization based on vbt information. Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-7-matthew.d.roper@intel.com
2021-05-15drm/i915: Get slice height before computing rc paramsVandita Kulkarni1-4/+4
We need slice height to calculate few RC parameters hence assign slice height first. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-6-matthew.d.roper@intel.com
2021-05-15drm/i915/xelpd: Support DP1.4 compression BPPsVandita Kulkarni1-8/+23
Support compression BPPs from bpc to uncompressed BPP -1. So far we have 8,10,12 as valid compressed BPPS now the support is extended. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-5-matthew.d.roper@intel.com
2021-05-15drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bppVandita Kulkarni1-10/+10
Move the platform specific max bpc calculation into intel_dp_dsc_compute_bpp function Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-4-matthew.d.roper@intel.com
2021-05-15drm/i915/xelpd: Increase maximum watermark lines to 255Matt Roper2-6/+12
XE_LPD continues to use the same "skylake-style" watermark programming as other recent platforms. The only change to the watermark calculations compared to Display12 is that XE_LPD now allows a maximum of 255 lines vs the old limit of 31. Due to the larger possible lines value, the corresponding bits representing the value in PLANE_WM are also extended, so make sure we read/write enough bits. Let's also take this opportunity to switch over to the REG_FIELD notation. Bspec: 49325 Bspec: 50419 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-3-matthew.d.roper@intel.com
2021-05-15drm/i915/xelpd: Handle new location of outputs D and EMatt Roper5-22/+74
The DDI naming template for display version 12 went A-C, TC1-TC6. With XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4. The XE_LPD design keeps the register offsets and bitfields relating to the TC outputs in the same location they were previously. The new "D" and "E" outputs now take the locations that were previously used by TC5 and TC6 outputs, or what we would have considered to be outputs "H" and "I" under the legacy lettering scheme. For the most part everything will just work as long as we initialize the output with the proper 'enum port' value. However we do need to take care to pick the correct AUX channel when parsing the VBT (e.g., a reference to 'AUX D' is actually asking us to use the 8th aux channel, not the fourth). We should also make sure that our encoders and aux channels are named appropriately so that it's easier to correlate driver debug messages with the bspec instructions. v2: - Update handling of TGL_TRANS_CLK_SEL_PORT. (Jose) v3: - Add hpd_pin to handle outputs D and E (Jose) - Fixed conversion of BIOS port to aux ch for TC ports (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-2-matthew.d.roper@intel.com
2021-05-14drm/i915: Merge fix for "drm: Switch to %p4cc format modifier"Stephen Rothwell1-4/+2
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Fixes: 92f1d09ca4ed ("drm: Switch to %p4cc format modifier") Cc: Sakari Ailus <sakari.ailus@linux.intel.com> Cc: Petr Mladek <pmladek@suse.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: dri-devel@lists.freedesktop.org Link: https://lore.kernel.org/dri-devel/20210514115307.4364aff9@canb.auug.org.au/T/#macc61d4e0b17ca0da2b26aae8fbbcbf47324da13
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-25 22:06:43 +0300