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path: root/drivers/gpu/drm/i915/intel_display.c
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2018-06-28Merge tag 'drm-intel-next-2018-06-20' of ↵Dave Airlie1-18/+104
git://anongit.freedesktop.org/drm/drm-intel into drm-next Chris is doing many reworks that allow us to get full-ppgtt supported on all platforms back to HSW. As well many other fix and improvements, Including: - Use GEM suspend when aborting initialization (Chris) - Change i915_gem_fault to return vm_fault_t (Chris) - Expand VMA to Non gem object entities (Chris) - Improve logs for load failure, but quite logging on fault injection to avoid noise on CI (Chris) - Other page directory handling fixes and improvements for gen6 (Chris) - Other gtt clean-up removing redundancies and unused checks (Chris) - Reorder aliasing ppgtt fini (Chris) - Refactor of unsetting obg->mm.pages (Chris) - Apply batch location restrictions before pinning (Chris) - Ringbuffer fixes for context restore (Chris) - Execlist fixes on freeing error pointer on allocation error (Chris) - Make closing request flush mandatory (Chris) - Move GEM sanitize from resume_early to resume (Chris) - Improve debug dumps (Chris) - Silent compiler for selftest (Chris) - Other execlists changes to improve hangcheck and reset. - Many gtt page directory fixes and improvements (Chris) - Reorg context workarounds (Chris) - Avoid ERR_PTR dereference on selftest (Chris) Other GEM related work: - Stop trying to reset GPU if reset failed (Mika) - Add HW workaround for KBL to fix GPU reset (Mika) - Fix context ban and hang accounting for client (Mika) - Fixes on OA perf (Michel, Jani) - Refactor on GuC log mechanisms (Piotr) - Enable provoking vertex fix on Gen9 system (Kenneth) More ICL patches for Display enabling: - ICL - 10-bit support for HDMI (RK) - ICL - Start adding TBT PLL (Paulo) - ICL - DDI HDMK level selection (Manasi) - ICL - GMBUS GPIO pin mapping fix (Mahesh) - ICL - Adding DP_AUX_E support (James) - ICL - Display interrupts handling (DK) Other display fixes and improvements: - Fix sprite destination color keying on SKL+ (Ville) - Fixes and improvements on PCH detection, specially for non PCH systems (Jani) - Document PCH_NOP (Lucas) - Allow DBLSCAN user modes with eDP/LVDS/DSI (Ville) - Opregion and ACPI cleanup and organization (Jani) - Kill delays when activation psr (Rodrigo) - ...and a consequent fix of the psr activation flow (DK) - Fix HDMI infoframe setting (Imre) - Fix Display interrupts and modes on old gens (Ville) - Start switching to kernel unsigned int types (Jani) - Introduction to Amber Lake and Whiskey Lake platforms (Jose) - Audio clock fixes for HBR3 (RK) - Standardize i915_reg.h definitions according to our doc and checkpatch (Paulo) - Remove unused timespec_to_jiffies_timeout function (Arnd) - Increase the scope of PSR wake fix for other VBTs out there (Vathsala) - Improve debug msgs with prop name/id (Ville) - Other clean up on unecessary cursor size defines (Ville) - Enforce max hdisplay/hblank_start limits on HSW/BDW (Ville) - Make ELD pointers constant (Jani) - Fix for PSR VBT parse (Colin) - Add warn about unsupported CDCLK rates (Imre) Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Thu 21 Jun 2018 07:12:10 AM AEST # gpg: using RSA key FA625F640EEB13CA # gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>" # gpg: aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C E2A3 FA62 5F64 0EEB 13CA Link: https://patchwork.freedesktop.org/patch/msgid/20180625165622.GA21761@intel.com
2018-06-22Merge tag 'drm-misc-next-2018-06-21' of ↵Dave Airlie1-40/+83
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 4.19: UAPI Changes: - Add writeback connector (Brian Starkey/Liviu Dudau) - Add "content type" property to HDMI connectors (Stanislav Lisovskiy) Cross-subsystem Changes: - some devicetree Docs update - fix compile breakage on ION due to the dma-buf cleanups (Christian König) Core Changes: - Reject over-sized allocation requests early (Chris Wilson) - gem-fb-helper: Always do implicit sync (Daniel Vetter) - dma-buf cleanups (Christian König) Driver Changes: - Fixes for the otm8009a panel driver (Philippe Cornu) - Add Innolux TV123WAM panel driver support (Sandeep Panda) - Move GEM BO to drm_framebuffer in few drivers (Daniel Stone) - i915 pinning improvements (Chris Wilson) - Stop consulting plane->fb/crtc in a few drivers (Ville Syrjälä) Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180621105428.GA20795@juma
2018-06-20Merge drm-upstream/drm-next into drm-misc-nextGustavo Padovan1-48/+216
We got a few conflicts in drm_atomic.c after merging the DRM writeback support, now we need a backmerge to unlock develop development on drm-misc-next. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
2018-06-19drm/i915: Check timings against hardware maximumsVille Syrjälä1-0/+35
Validate that all display timings fit within the number of bits we have in the transcoder timing registers. The limits are: hsw+: 4k: vdisplay, vblank_start 8k: everything else gen3+: 4k: h/vdisplay, h/vblank_start 8k: everything else gen2: 2k: h/vdisplay, h/vblank_start 4k: everything else Also document the fact that the mode_config.max_width/height limits refer to just the max framebuffer dimensions we support. Which may be larger than the max hdisplay/vdisplay. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-2-ville.syrjala@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2018-06-19drm/i915: Nuke the cursor size definesVille Syrjälä1-4/+4
No point in having this extra indireciton for the cursor max size. So drop the defines and just write out the raw numbers. Makes it easier to see what's going on. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-1-ville.syrjala@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2018-06-15drm/i915/icl: unconditionally init DDI for every portPaulo Zanoni1-1/+8
On ICP, port present straps (from SFUSE_STRAP PCH register) are no longer supported. Software should determine the presence through BIOS VBT, hotplug or other mechanisms. v2: Improve commit message (Lucas). Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-14-paulo.r.zanoni@intel.com
2018-06-15drm/i915/icl: add icelake_get_ddi_pll()Paulo Zanoni1-1/+41
Implement the hardware state readout code. Thanks to Animesh Manna for spotting this problem. Cc: Animesh Manna <animesh.manna@intel.com> Credits-to: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-11-paulo.r.zanoni@intel.com
2018-06-14drm/i915/ddi: Push pipe clock enabling to encodersImre Deak1-6/+0
On ICL the pipe clock needs to be enabled before setting the HDMI infoframe, but these steps are in the reverse order atm. Move the pipe clock enabling to the encoders, so reordering of the two steps can be done in a clean way. No functional change. v2: - Rebased on drm-tip. Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180613172746.18525-1-imre.deak@intel.com
2018-06-14drm/i915/ddi: s/crtc->config/old_crtc_state in haswell_crtc_disable()Imre Deak1-4/+4
crtc->config points to the old crtc state at the point display.crtc_disable() is called, so use the more descriptive pointer instead. v2: - Convert one remaining instance of the ptr in the function. (Ville) Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180613170710.15080-2-imre.deak@intel.com
2018-06-13drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSIVille Syrjälä1-3/+13
When encountering a connector with the scaling mode property both intel and modesetting ddxs sometimes add tons of DBLSCAN modes to the output's mode list. The idea presumably being that since the output will be going through the panel fitter anyway we can pretend to use any kind of mode. Sadly that means we can't reject user modes with the DBLSCAN flag until we know whether we're going to be using the panel's native mode or the user mode directly. Doing otherwise means X clients using xf86vidmode/xrandr will get a protocol error (and often self terminate as a result) when the kernel refuses to use the requested mode with the DBLSCAN flag. To undo the regression we'll move the DBLSCAN checks into the connector->mode_valid() and encoder->compute_config() hooks. Cc: stable@vger.kernel.org Cc: Vito Caputo <vcaputo@pengaru.com> Reported-by: Vito Caputo <vcaputo@pengaru.com> Fixes: e995ca0b8139 ("drm/i915: Provide a device level .mode_valid() hook") References: https://lkml.org/lkml/2018/5/21/715 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180524125403.23445-1-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106804 Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
2018-06-11drm/i915: Stop updating plane->fb/crtcVille Syrjälä1-4/+3
We want to get rid of plane->fb/crtc on atomic drivers. Stop setting them. v2: Fix up the comment in intel_crtc_active() and nuke the rest of the stale comments (Daniel) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v1 Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20180525185045.29689-9-ville.syrjala@linux.intel.com Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2018-06-07drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setupVille Syrjälä1-6/+1
We already handle the color encoding mode properly. Remove the broken NV12 special case. Cc: Vidya Srinivas <vidya.srinivas@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: 8ed30ab6aced ("drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180521185613.5097-1-ville.syrjala@linux.intel.com Reviewed-By: Vidya Srinivas <vidya.srinivas@intel.com> (cherry picked from commit 012d79e6a33f095c293fe2a02b2b3b26d8c6402c) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2018-06-02drm/i915/icl: introduce tc_portPaulo Zanoni1-0/+16
Add and enum for TC ports and auxiliary functions to handle them. Icelake brings a lot of registers and other things that only apply to the TC ports and are indexed starting from 0, so having an enum for tc_ports that starts at 0 really helps the indexing. This patch is based on previous patches written by Dhinakaran Pandiyan and Mahesh Kumar. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-4-paulo.r.zanoni@intel.com
2018-06-01drm/i915: Configure SKL+ scaler initial phase correctlyVille Syrjälä1-0/+41
Set up the SKL+ scaler initial phase registers correctly. Otherwise we start fetching the data from the center of the first pixel instead of the top-left corner, which obviously then leads to right/bottom edges replicating data excessively as the data runs out half a pixel too soon. Cc: Vidya Srinivas <vidya.srinivas@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180521185613.5097-2-ville.syrjala@linux.intel.com Reviewed-By: Vidya Srinivas <vidya.srinivas@intel.com>
2018-06-01drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setupVille Syrjälä1-6/+1
We already handle the color encoding mode properly. Remove the broken NV12 special case. Cc: Vidya Srinivas <vidya.srinivas@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: 8ed30ab6aced ("drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180521185613.5097-1-ville.syrjala@linux.intel.com Reviewed-By: Vidya Srinivas <vidya.srinivas@intel.com>
2018-06-01drm/i915: Disable trickle feed for SNB/IVB cursorsVille Syrjälä1-0/+3
We disable trickle feed whenever possible, except for the cursors on SNB/IVB. Let's try disabling it there too if for no other reason than consistency. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130203807.13721-5-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2018-06-01drm/i915: Clean up cursor definesVille Syrjälä1-8/+8
Use MCURSOR_ instead of CURSOR_ as the prefix for the non-845/865 cursor defines consistently, and move the pipe CSC enable bit next to the other non-845/865 cursor defines. v2: Take care of gvt uses as well v3: Another gvt use popped up Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180131143709.875-1-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com> #v2
2018-06-01drm/i915: Have plane->get_hw_state() return the current pipeVille Syrjälä1-20/+51
Like we do for encoder let's make the plane->get_hw_state() return the pipe to which the plane is currently attached. We don't currently allow planes to move between the pipes, but perhaps one day we will. In either case this makes the code more uniform and perhaps makes intel_plane_mapping_ok() slightly more clear. Note that for i965 and g4x planes A and B still have pipe select bits but they're hardwired to pipe A and B respectively. This means we can safely interpret those bits just like on gen2/3. This allows the same readout code work for plane C (which can still be assigned to eiter pipe on i965) should we ever expose it. g4x no longer allows moving the cursor planes between the pipes, but the pipe select bits can still be set in the register. Thus we have to ignore those bits. OTOH i965 still allows the cursors to move between pipes thus we have to trust the bits there. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130203807.13721-3-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2018-05-31drm/i915: Call intel_opregion_notify_encoder in intel_sanitize_encoder, v2.Maarten Lankhorst1-0/+3
Normally this is called on a modeset, but the call is missing when we inherit the mode from the BIOS, so make sure it's called somewhere in hardware readout. Changes since v1: - Unconditionally call intel_opregion_notify_encoder. (Ville) Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180516085038.36785-1-maarten.lankhorst@linux.intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2018-05-30drm/i915: Promote .format_mod_supported() to the lead roleVille Syrjälä1-36/+80
Up to now we've used the plane's modifier list as the primary source of information for which modifiers are supported by a given plane. In order to allow auxiliary metadata to be embedded within the bits of the modifier we need to stop doing that. Thus we have to make .format_mod_supported() aware of the plane's capabilities and gracefully deal with any modifier being passed in directly from userspace. v2: Rebase after NV12 Simplify Cc: Eric Anholt <eric@anholt.net> References: https://lists.freedesktop.org/archives/dri-devel/2018-March/169782.html Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180518162159.30305-1-ville.syrjala@linux.intel.com Reviewed-by: Eric Anholt <eric@anholt.net>
2018-05-25drm/i915: Simplify ilk-ivb underrun suppressionVille Syrjälä1-8/+4
Let's suppress the underruns around every modeset sequence instead of trying to avoid it. Planes are disabled at this point anyway so we don't really gain anything from keeping the underrun reporting enabled. Also for PCH ports we already suppress all underruns here anyway so trying avoid it for the CPU eDP doesn't seem all that important. Maybe this gets rid of some lingering spurious underruns? Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180524190406.2973-2-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-05-25drm/i915: Try to suppress more spurious PCH underruns on ILK-IVBVille Syrjälä1-2/+9
My ILK seems to generate a spurious PCH underrun with most interlaced HDMI modes. Add a second vblank wait to avoid it. We have seen some spurious PCH underruns still in CI as well, some of which seem to be progressive DP. The logs also point towards some spurious underrins with progressive HDMI on SNB. While I don't have a solid explanation for those let's try to kill all the birds with one stone and always do the double wait. Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106387 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180524190406.2973-1-ville.syrjala@linux.intel.com Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-05-25drm/i915: Initialize panel_pipe to INVALID_PIPEVille Syrjälä1-1/+1
We can always figure out which pipe is affected by the panel power sequencer lockout mechanism. So no need for the pipe A fallback anymore. The only case we may have to worry about is an invalid port select in the power sequencer, but INVALID_PIPE is just fine in that case. We'll get the WARN about the bogus pps port select anyway. Cc: Jani Nikula <jani.nikula@intel.com> Suggested-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180523145718.22932-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2018-05-23drm/i915/icl: Disable pipe CSC and gamma in cursor planeJosé Roberto de Souza1-4/+6
'Pipe CSC enable' bit is more than just deprecated in ICL+, it was disabled in commit 077ef1f09c25 ("drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL") for primary and sprite planes as it was causing those planes to be rendered as always black but it was not disabled in cursor plane, also causing it to be rendered as black. As mentioned in the commit referenced above, this is a workaround too and the CSC and gamma per plane values needs to be setup before enable CSC and gamma again. BSpec: 4278 and 7635 Cc: James Ausmus <james.ausmus@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180518201547.15793-1-jose.souza@intel.com
2018-05-23drm/i915: WARN if power sequencer is not connected to the LVDS port on pre-ilkVille Syrjälä1-0/+5
We don't support using the power sequencer with other ports besides LVDS on pre-ilk platforms. WARN if someone has mistakenly connected the power sequencer to the wrong port. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180518152931.13104-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2018-05-23drm/i915: Implement the missing bits of assert_panel_unlocked()Ville Syrjälä1-2/+16
Add the missing eDP port handling into assert_panel_unlocked(). We now have intel_dp_port_enabled() which makes this trivial. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180518152931.13104-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2018-05-23drm/i915: Clean up DP pipe select bitsVille Syrjälä1-31/+15
Clean up the DP pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state(), the port state asserts, and the VLV power sequencer code. v2: Return PIPE_A for cpt/ppt when the port isn't selected by any transcoder. Returning INVALID_PIPE explodes *somewhere* on some machines (can't immediately see where though). This now matches the old behaviour. v3: Order the defines shift,mask,value (Jani) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180518152931.13104-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2018-05-23drm/i915: Nuke intel_trans_dp_port_sel()Ville Syrjälä1-25/+14
for_each_encoder_on_crtc() is legacy and shouldn't be used by atomic drivers. Let's throw out intel_trans_dp_port_sel() and replace it with intel_get_crtc_new_encoder() which looks the atomic state instead. Since we now have to call intel_get_crtc_new_encoder() during the commit phase we'll need to plumb in the top level atomic state. The crtc_state->state pointers are no longer valid at that point. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180518152931.13104-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2018-05-23drm/i915: Parametrize TRANS_DP_PORT_SELVille Syrjälä1-16/+8
Parametrize the TRANS_DP_PORT_SEL macros. v2: WARN for bogus ports (Jani) Order the defines mask,value (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180518152931.13104-2-ville.syrjala@linux.intel.com
2018-05-23drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi codeVille Syrjälä1-1/+30
The ddi code no longer uses intel_ddi_get_crtc_new_encoder(). Move it elsewhere where we have some users left. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180518152931.13104-1-ville.syrjala@linux.intel.com
2018-05-22drm/i915: Move GEM BO inside drm_framebufferDaniel Stone1-2/+2
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. v2: Only hold a single reference per framebuffer, not per plane. (Ville) v3: Drop NULL check in intel_fb_obj. (Ville) Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Ville Syrjälä <ville.syrjala@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org Link: https://patchwork.freedesktop.org/patch/msgid/20180518143008.4120-2-daniels@collabora.com
2018-05-22drm/i915: Use intel_fb_obj() everywhereDaniel Stone1-9/+10
We already have a macro to pull the GEM object from a FB, so use it everywhere. We'll make use of this later to move the object storage. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Ville Syrjälä <ville.syrjala@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org Link: https://patchwork.freedesktop.org/patch/msgid/20180518143008.4120-1-daniels@collabora.com
2018-05-18drm/i915: enable the pipe/transcoder/planes later on HSW+Paulo Zanoni1-5/+5
For all platforms that run haswell_crtc_enable, our spec tells us to configure the transcoder clocks and do link training before it tells us to set pipeconf and the other pipe/transcoder/plane registers. Starting from Icelake, we get machine hangs if we try to touch the pipe/transcoder registers without having the clocks configured and not having some chicken bits set. So this patch changes haswell_crtc_enable() to issue the calls at the appropriate order mandated by the spec. While setting the appropriate chicken bits would also work here, it's better if we actually program the hardware the way it is intended to be programmed. And the chicken bit also has some theoretical downsides that may or may not affect us. Also, correctly programming the hardware does not prevent us from setting the chicken bits in a later patch in case we decide to. v2: Don't forget link training (Ville). Cc: Arthur J Runyan <arthur.j.runyan@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180502215851.30736-1-paulo.r.zanoni@intel.com
2018-05-17drm/i915: Clean up SDVO pipe select bitsVille Syrjälä1-30/+16
Clean up the SDVO pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. v2: Order the defines shift,mask,value (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180514172423.9302-3-ville.syrjala@linux.intel.com
2018-05-17drm/i915: Clean up LVDS pipe select bitsVille Syrjälä1-26/+7
Clean up the LVDS pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. v2: Order the defines shift,mask,value (Jani) Drop ruperfluous braces and whitesapce changes (Jani) Combine masks in compute_is_dual_link_lvds() (Jani) v3: Fix LVDS_PIPE_SEL_MASK_CPT Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180514182827.28629-1-ville.syrjala@linux.intel.com
2018-05-17drm/i915: Clean up ADPA pipe select bitsVille Syrjälä1-19/+5
Clean up the ADPA pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. v2: Order the defines shift,mask,value (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180514172423.9302-1-ville.syrjala@linux.intel.com
2018-05-11drm/i915: Add NV12 as supported format for primary planeChandra Konduru1-2/+48
This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing skl_primary_formats v5: Rebased (me) v6: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v7: Review comments by Ville addressed Restricting the NV12 for BXT and on PIPE A and B Rebased (me) v8: Rebased (me) Modified restricting the NV12 support for both BXT and KBL. v9: Rebased (me) v10: Addressed review comments from Maarten. Adding NV12 inside skl_primary_formats itself. v11: Adding Reviewed By tag from Shashank Sharma v12: Addressed review comments from Juha-Pekka Heikkila "NV12 not to be supported by SKL" v13: Addressed review comments from Ville Added skl_pri_planar_formats to include NV12 and skl_plane_has_planar function to check for NV12 support on plane. Added NV12 format to skl_mod_supported. These were review comments from Kristian Høgsberg <hoegsberg@gmail.com> v14: Added reviewed by from Juha-Pekka Heikkila v15: Rebased the series v16: Added all tiling support under mod supported for NV12. Credits to Megha Aggarwal v17: Added RB by Maarten and Kristian v18: Review comments from Maarten addressed - Removing BROXTON support for NV12 due to WA826 v19: Addressed review comments from Maarten Make changes to skl_mod_supported Credits-to: Megha Aggarwal megha.aggarwal@intel.com Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-6-git-send-email-vidya.srinivas@intel.com
2018-05-11drm/i915: Add NV12 support to intel_framebuffer_initChandra Konduru1-0/+22
This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in intel_framebuffer_init Removed offset checks for NV12 case v5: Addressed review comments by Clinton A Taylor This NV12 support only correctly works on SKL. Plane color space conversion is different on GLK and later platforms causing the colors to display incorrectly. Ville's plane color space property patch series in review will fix this issue. - Restricted the NV12 case in intel_framebuffer_init to SKL and BXT only. v6: Rebased (me) v7: Addressed review comments by Ville Restricting the NV12 to BXT for now. v8: Rebased (me) Restricting the NV12 changes to BXT and KBL for now. v9: Rebased (me) v10: NV12 supported by all GEN >= 9. Making this change in intel_framebuffer_init. This is part of addressing Maarten's review comments. Comment under v8 no longer applicable v11: Addressed review comments from Shashank Sharma v12: Adding Reviewed By from Shashank Sharma v13: Addressed review comments from Juha-Pekka Heikkila "NV12 not to be supported by SKL" v14: Addressed review comments from Maarten. Add checks for fb width height for NV12 and fail the fb creation if check fails. Added reviewed by from Juha-Pekka Heikkila v15: Rebased the series v16: Setting the minimum value during fb creating to 16 as per Bspec for NV12. Earlier minimum was expected to be > 16. Now changed it to >=16. v17: Adding restriction to framebuffer_init - the fb width and height should be a multiplier of 4 v18: Added RB from Maarten. Included Maarten's review comments Dont allow CCS formats for fb creation of NV12 v19: Review comments from Maarten addressed - Removing BROXTON support for NV12 due to WA826 Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-5-git-send-email-vidya.srinivas@intel.com
2018-05-11drm/i915: Add skl_check_nv12_surface for NV12Maarten Lankhorst1-2/+27
We skip src trunction/adjustments for NV12 case and handle the sizes directly. Without this, pipe fifo underruns are seen on APL/KBL. v2: For NV12, making the src coordinates multiplier of 4 v3: Moving all the src coords handling code for NV12 to skl_check_nv12_surface v4: Added RB from Mika v5: Rebased the series. Removed checks of mult of 4 in skl_update_scaler, Added NV12 condition in intel_check_sprite_plane where src x/w is being checked for mult of 2 for yuv planes. v6: Made changes to skl_check_nv12_surface as per WA#1106 Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-4-git-send-email-vidya.srinivas@intel.com
2018-05-11drm/i915: Enable Display WA 0528Vidya Srinivas1-3/+19
Possible hang with NV12 plane surface formats. WA: When the plane source pixel format is NV12, the CHICKEN_PIPESL_* register bit 22 must be set to 1 and the render decompression must not be enabled on any of the planes in that pipe. v2: removed unnecessary POSTING_READ v3: Added RB from Maarten v4: Removed support for NV12 for BROXTON Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-3-git-send-email-vidya.srinivas@intel.com
2018-05-11drm/i915: Enable display workaround 827 for all planes, v2.Maarten Lankhorst1-17/+26
The workaround was applied only to the primary plane, but is required on all planes. Iterate over all planes in the crtc atomic check to see if the workaround is enabled, and only perform the actual toggling in the pre/post plane update functions. Changes since v1: - Track active NV12 planes in a nv12_planes bitmask. (Ville) v2: Removing BROXTON support for NV12 due to WA826 Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-2-git-send-email-vidya.srinivas@intel.com
2018-05-08drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni1-0/+16
This commit introduces the definitions for the ICL clocks and adds the basic functions to the shared DPLL framework. It adds code for the Enable and Disable sequences for some PLLs, but it does not have the code to compute the actual PLL values, which are marked as TODO comments and should be introduced as separate commits. Special thanks to James Ausmus for investigating and fixing a bug with the placement of icl_unmap_plls_to_ports() function. v2: - Rebase around dpll_lock changes. v3: - The spec now says what the timeouts should be. - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze the machine. - Checkpatch found a white space problem. - Small adjustments before upstreaming. v4: - Move the ICL checks out of the *map_plls_to_ports() functions (James) - Add extra encoder check (James) - Call icl_unmap_plls_to_ports() later (James) v5: - Rebase after the pll struct changes. v6: - Properly make the unmap function based on encoders_post_disable() with regarding to checks and iterators. - Address checkpatch comment on "min = max = x()". Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180427231436.9353-1-paulo.r.zanoni@intel.com
2018-05-04Merge tag 'drm-intel-next-2018-04-13' of ↵Dave Airlie1-80/+171
git://anongit.freedesktop.org/drm/drm-intel into drm-next First drm/i915 feature batch heading for v4.18: - drm-next backmerge to fix build (Rodrigo) - GPU documentation improvements (Kevin) - GuC and HuC refactoring, host/GuC communication, logging, fixes, and more (mostly Michal and Michał, also Jackie, Michel and Piotr) - PSR and PSR2 enabling and fixes (DK, José, Rodrigo and Chris) - Selftest updates (Chris, Daniele) - DPLL management refactoring (Lucas) - DP MST fixes (Lyude and DK) - Watermark refactoring and changes to support NV12 (Mahesh) - NV12 prep work (Chandra) - Icelake Combo PHY enablers (Manasi) - Perf OA refactoring and ICL enabling (Lionel) - ICL enabling (Oscar, Paulo, Nabendu, Mika, Kelvin, Michel) - Workarounds refactoring (Oscar) - HDCP fixes and improvements (Ramalingam, Radhakrishna) - Power management fixes (Imre) - Various display fixes (Maarten, Ville, Vidya, Jani, Gaurav) - debugfs for FIFO underrun clearing (Maarten) - Execlist improvements (Chris) - Reset improvements (Chris) - Plenty of things here and there I overlooked and/or didn't understand... (Everyone) Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/87lgd2cze8.fsf@intel.com
2018-05-03drm/i915: Correctly populate user mode h/vdisplay with pipe src size during ↵Ville Syrjälä1-0/+2
readout During state readout we first read out the pipe src size, store that information in the user mode h/vdisplay, but later on we overwrite that with the actual crtc timings. That makes our read out crtc state inconsistent with itself when the BIOS has enabled the panel fitter to scale the pipe contents. Let's preserve the pipe src size based information in the user mode to make things consistent again. This fixes a problem introduced by commit a2936e3d9a9c ("drm/i915: Use drm_mode_get_hv_timing() to populate plane clip rectangle") where the inconsistent state is now leading the plane clipping code to report a failure on account the plane dst coordinates not matching the user mode size. Previously we did the plane clipping based on the pipe src size instead and thus never noticed the inconsistency. The failure manifests as a WARN: [ 0.762117] [drm:intel_dump_pipe_config [i915]] requested mode: [ 0.762142] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1366x768" 60 72143 1366 1414 1446 1526 768 771 777 784 0x40 0xa ... [ 0.762327] [drm:intel_dump_pipe_config [i915]] port clock: 72143, pipe src size: 1024x768, pixel rate 72143 ... [ 0.764666] [drm:drm_atomic_helper_check_plane_state [drm_kms_helper]] Plane must cover entire CRTC [ 0.764690] [drm:drm_rect_debug_print [drm]] dst: 1024x768+0+0 [ 0.764711] [drm:drm_rect_debug_print [drm]] clip: 1366x768+0+0 [ 0.764713] ------------[ cut here ]------------ [ 0.764714] Could not determine valid watermarks for inherited state [ 0.764792] WARNING: CPU: 4 PID: 159 at drivers/gpu/drm/i915/intel_display.c:14584 intel_modeset_init+0x3ce/0x19d0 [i915] ... Cc: FadeMind <fademind@gmail.com> Cc: Dave Jones <davej@codemonkey.org.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reported-by: FadeMind <fademind@gmail.com> Reported-by: Dave Jones <davej@codemonkey.org.uk> Tested-by: Dave Jones <davej@codemonkey.org.uk> References: https://lists.freedesktop.org/archives/intel-gfx/2018-April/163186.html Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105992 Fixes: a2936e3d9a9c ("drm/i915: Use drm_mode_get_hv_timing() to populate plane clip rectangle") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180426163015.14232-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Larry Finger <Larry.Finger@lwfinger.net> Tested-by: FadeMind <fademind@gmail.com>
2018-05-02Merge drm/drm-next into drm-intel-next-queuedJani Nikula1-1/+3
Need d224985a5e31 ("sched/wait, drivers/drm: Convert wait_on_atomic_t() usage to the new wait_var_event() API") in dinq to be able to fix https://bugs.freedesktop.org/show_bug.cgi?id=106085. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2018-04-28drm/i915/icl: Enable 2nd DBuf slice only when neededMahesh Kumar1-0/+10
ICL has two slices of DBuf, each slice of size 1024 blocks. We should not always enable slice-2. It should be enabled only if display total required BW is > 12GBps OR more than 1 pipes are enabled. Changes since V1: - typecast total_data_rate to u64 before multiplication to solve any possible overflow (Rodrigo) - fix where skl_wm_get_hw_state was memsetting ddb, resulting enabled_slices to become zero - Fix the logic of calculating ddb_size Changes since V2: - If no-crtc is part of commit required_slices will have value "0", don't try to disable DBuf slice. Changes since V3: - Create a generic helper to enable/disable slice - don't return early if total_data_rate is 0, it may be cursor only commit, or atomic modeset without any plane. Changes since V4: - Solve checkpatch warnings - use kernel types u8/u64 instead of uint8_t/uint64_t Changes since V5: - Rebase Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-3-mahesh1.kumar@intel.com
2018-04-28drm/i915/icl: track dbuf slice-2 statusMahesh Kumar1-0/+5
This patch adds support to start tracking status of DBUF slices. This is foundation to introduce support for enabling/disabling second DBUF slice dynamically for ICL. Changes Since V1: - use kernel type u8 over uint8_t Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-2-mahesh1.kumar@intel.com
2018-04-27drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTLJames Ausmus1-2/+6
These fields have been deprecated and moved in ICL+. Stop setting the bits. They have moved to GAMMA_MODE and CSC_MODE, respectively. This patch is just to stop incorrectly setting bits in PLANE_COLOR_CTL while we're waiting for the new replacement functionality to be done. v2: Drop useless comment, and change !(GEN >= 11) to (GEN < 11). (Ville) v3: No changes v4 (from Paulo): Rebase. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180328215803.13835-2-paulo.r.zanoni@intel.com
2018-04-19drm/i915: Protect PIPE_CONF_CHECK macros with do {} while(0)Ville Syrjälä1-18/+27
Make the PIPE_CONF_CHECK macros a bit more robust by wrapping them in do {} while(0). Avoids funky sirprises when you try put an 'else' after a PIPE_CONF_CHECK invocation... Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180316183625.16316-1-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
2018-04-18drm/i915: Pack params to engine->schedule() into a structChris Wilson1-1/+10
Today we only want to pass along the priority to engine->schedule(), but in the future we want to have much more control over the various aspects of the GPU during a context's execution, for example controlling the frequency allowed. As we need an ever growing number of parameters for scheduling, move those into a struct for convenience. v2: Move the anonymous struct into its own function for legibility and ye olde gcc. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180418184052.7129-3-chris@chris-wilson.co.uk
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-05 00:47:54 +0300