| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-07-05 | drm/i915: Mark expected switch fall-throughs | Gustavo A. R. Silva | 1 | -0/+5 |
| 2018-06-16 | drm/i915/icl: implement DVFS for ICL | Paulo Zanoni | 1 | -3/+43 |
| 2018-06-11 | drm/i915/skl: Add warn about unsupported CDCLK rates | Imre Deak | 1 | -0/+10 |
| 2018-05-03 | drm/i915: Adjust eDP's logical vco in a reliable place. | Rodrigo Vivi | 1 | -4/+37 |
| 2018-04-23 | drm/i915/audio: set minimum CD clock to twice the BCLK | Abhay Kumar | 1 | -2/+14 |
| 2018-04-05 | Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jik... | Linus Torvalds | 1 | -2/+2 |
| 2018-03-27 | treewide: Fix typos in printk | Masanari Iida | 1 | -2/+2 |
| 2018-02-14 | drm/i915/vlv: Add cdclk workaround for DSI | Hans de Goede | 1 | -0/+8 |
| 2018-02-13 | drm/i915/icl: add the main CDCLK functions | Paulo Zanoni | 1 | -2/+235 |
| 2018-02-10 | drm/i915: Use INTEL_GEN everywhere | Tvrtko Ursulin | 1 | -1/+1 |
| 2018-02-06 | drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing | Imre Deak | 1 | -5/+17 |
| 2018-02-01 | drm/i915/bxt, glk: Avoid long atomic poll during CDCLK change | Imre Deak | 1 | -2/+2 |
| 2018-02-01 | drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing | Imre Deak | 1 | -5/+17 |
| 2018-01-19 | drm/i915/icp: Get/set proper Raw clock frequency on ICP | Anusha Srivatsa | 1 | -2/+27 |
| 2018-01-18 | drm/i915: Add tracking for CDCLK bypass frequency | Imre Deak | 1 | -17/+18 |
| 2018-01-18 | BackMerge tag 'v4.15-rc8' into drm-next | Dave Airlie | 1 | -9/+26 |
| 2018-01-04 | drm/i915: Apply Display WA #1183 on skl, kbl, and cfl | Lucas De Marchi | 1 | -9/+26 |
| 2017-12-23 | drm/i915/vlv: Add cdclk workaround for DSI | Hans de Goede | 1 | -0/+8 |
| 2017-12-23 | drm/i915: Apply Display WA #1183 on skl, kbl, and cfl | Lucas De Marchi | 1 | -9/+26 |
| 2017-11-30 | drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3. | Maarten Lankhorst | 1 | -1/+1 |
| 2017-10-25 | drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. | Rodrigo Vivi | 1 | -12/+2 |
| 2017-10-25 | drm/i915: Perform a central cdclk state sanity check | Ville Syrjälä | 1 | -11/+19 |
| 2017-10-25 | drm/i915: Sanity check cdclk in vlv_set_cdclk() | Ville Syrjälä | 1 | -0/+12 |
| 2017-10-25 | drm/i915: Adjust system agent voltage on CNL if required by DDI ports | Ville Syrjälä | 1 | -1/+45 |
| 2017-10-25 | drm/i915: Use cdclk_state->voltage on CNL | Ville Syrjälä | 1 | -16/+31 |
| 2017-10-25 | drm/i915: Use cdclk_state->voltage on BXT/GLK | Ville Syrjälä | 1 | -2/+21 |
| 2017-10-25 | drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL | Ville Syrjälä | 1 | -7/+36 |
| 2017-10-25 | drm/i915: Use cdclk_state->voltage on BDW | Ville Syrjälä | 1 | -6/+29 |
| 2017-10-25 | drm/i915: Use cdclk_state->voltage on VLV/CHV | Ville Syrjälä | 1 | -16/+38 |
| 2017-10-25 | drm/i915: Start tracking voltage level in the cdclk state | Ville Syrjälä | 1 | -7/+24 |
| 2017-10-25 | drm/i915: Clean up some cdclk switch statements | Ville Syrjälä | 1 | -34/+34 |
| 2017-10-11 | drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock | Sagar Arun Kamble | 1 | -20/+20 |
| 2017-09-12 | drm/i915: Increase poll time for BDW FCLK_DONE | Marta Lofstedt | 1 | -1/+5 |
| 2017-08-31 | drm/i915: Consolidate max_cdclk_freq check in intel_crtc_compute_min_cdclk() | Ville Syrjälä | 1 | -52/+44 |
| 2017-08-31 | drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock" | Ville Syrjälä | 1 | -98/+104 |
| 2017-06-29 | drm/i915: reintroduce VLV/CHV PFI programming power domain workaround | Gabriel Krisman Bertazi | 1 | -0/+20 |
| 2017-06-12 | drm/i915/cnl: Allow dynamic cdclk changes on CNL | Rodrigo Vivi | 1 | -4/+56 |
| 2017-06-12 | drm/i915/cnl: Implement CNL display init/unit sequence | Ville Syrjälä | 1 | -1/+107 |
| 2017-06-12 | drm/i915/cnl: Implement .set_cdclk() for CNL | Ville Syrjälä | 1 | -0/+106 |
| 2017-06-12 | drm/i915/cnl: Implement .get_display_clock_speed() for CNL | Ville Syrjälä | 1 | -1/+55 |
| 2017-06-02 | drm/i915/cnp: Get/set proper Raw clock frequency on CNP. | Rodrigo Vivi | 1 | -1/+28 |
| 2017-05-05 | drm/i915: Fix rawclk readout for g4x | Ville Syrjälä | 1 | -4/+2 |
| 2017-04-06 | drm/i915/glk: limit pixel clock to 99% of cdclk workaround | Madhav Chauhan | 1 | -3/+13 |
| 2017-03-22 | drm/i915: Implement cdclk restrictions based on Azalia BCLK | Pandiyan, Dhinakaran | 1 | -0/+12 |
| 2017-03-22 | drm/i915/glk: Apply cdclk workaround for DP audio | Pandiyan, Dhinakaran | 1 | -6/+11 |
| 2017-03-13 | drm/i915: Use new atomic iterator macros in cdclk | Maarten Lankhorst | 1 | -1/+1 |
| 2017-03-07 | drm/i915: remove potentially confusing IS_G4X checks | Paulo Zanoni | 1 | -2/+2 |
| 2017-02-08 | drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cd... | Ville Syrjälä | 1 | -46/+33 |
| 2017-02-08 | drm/i915: Nuke the VLV/CHV PFI programming power domain workaround | Ville Syrjälä | 1 | -14/+0 |
| 2017-02-08 | drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk() | Ville Syrjälä | 1 | -1/+4 |
