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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2012-10-12drm/i915: Set guardband clipping workaround bit in the right register.Kenneth Graunke1-1/+1
2012-10-04drm/i915: Fix GT_MODE default valueBen Widawsky1-0/+3
2012-09-26drm/i915: make sure we write all the DIP data bytesPaulo Zanoni1-0/+4
2012-09-07Merge the modeset-rework, basic conversion into drm-intel-nextDaniel Vetter1-0/+2
2012-09-06drm/i915/dp: implement get_hw_stateDaniel Vetter1-0/+2
2012-09-03Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel ...Dave Airlie1-0/+79
2012-08-27Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torval...Dave Airlie1-0/+1
2012-08-24drm/i915: Add new INSTDONE registersBen Widawsky1-1/+5
2012-08-24drm/i915: Extract reading INSTDONEBen Widawsky1-0/+1
2012-08-22drm/i915: Find unclaimed MMIO writes.Ben Widawsky1-0/+1
2012-08-22drm/i915: Add ERR_INT to gen7 error stateBen Widawsky1-0/+1
2012-08-17drm/i915: ironlake_write_eld code cleanupWang Xingchao1-0/+25
2012-08-17drm/i915: HSW audio registers definitionWang Xingchao1-0/+47
2012-08-17drm/i915: fix hsw uncached pteDaniel Vetter1-0/+1
2012-08-09drm/i915: add parentheses around PIXCLK_GATE definitionsPaulo Zanoni1-2/+2
2012-08-09drm/i915: reindent Haswell register definitionsPaulo Zanoni1-99/+85
2012-08-09drm/i915: correctly set the DDI_FUNC_CTL bpc fieldPaulo Zanoni1-0/+1
2012-08-09drm/i915: set the DDI sync polarity bitsPaulo Zanoni1-0/+2
2012-08-09drm/i915: fix pipe DDI mode selectPaulo Zanoni1-0/+1
2012-07-25drm/i915: Add contexts for HSWBen Widawsky1-0/+8
2012-07-25drm/i915: add inte_crt->adpa_regDaniel Vetter1-0/+1
2012-07-25drm/i915: create VLV_DSIPLAY_BASE #defineDaniel Vetter1-0/+2
2012-07-25drm/i915: add register read IOCTLBen Widawsky1-0/+1
2012-07-25drm/i915: group ADPA #defines togetherDaniel Vetter1-25/+22
2012-07-20drm/i915: fix up PCH backlight #define mixupDaniel Vetter1-1/+1
2012-07-20drm/i915: Add comments to explain the BSD tail write workaroundChris Wilson1-4/+4
2012-07-20drm/i915/context: Add missing IVB context sizesBen Widawsky1-1/+5
2012-07-20drm/i915/context/: s/CTX/CXTBen Widawsky1-9/+9
2012-07-05drm/i915: program FDI_RX TP and FDI delaysEugeni Dodonov1-0/+3
2012-07-05drm/i915: adjust framebuffer base address on gen4+Daniel Vetter1-1/+1
2012-07-05drm/i915: introduce crtc->dspaddr_offsetDaniel Vetter1-0/+1
2012-07-05drm/i915: fix PIPE_DDI_PORT_MASKPaulo Zanoni1-1/+1
2012-07-05drm/i915: enable RC6 workaround on HaswellEugeni Dodonov1-0/+5
2012-07-05drm/i915: add RPS configuration for HaswellEugeni Dodonov1-0/+1
2012-07-04drm/i915: support Haswell force wakingEugeni Dodonov1-0/+1
2012-07-04drm/i915: Implement w/a for sporadic read failures on waking from rc6Chris Wilson1-0/+4
2012-06-28drm/i915: fix PIPE_WM_LINETIME definitionPaulo Zanoni1-1/+1
2012-06-25Merge tag 'v3.5-rc4' into drm-intel-next-queuedDaniel Vetter1-3/+40
2012-06-21drm/i915: enable display messages to GT on ValleyViewJesse Barnes1-2/+2
2012-06-20drm/i915: add HDMI and DP port enumeration on ValleyViewJesse Barnes1-1/+0
2012-06-20drm/i915: Enable DP panel power sequencing for ValleyViewShobhit Kumar1-0/+13
2012-06-20drm/i915: ValleyView mode setting limits and PLL functionsJesse Barnes1-0/+1
2012-06-18drm/i915: add L3 bank clock gating disable on VLVJesse Barnes1-0/+3
2012-06-18drm/i915: add TDL unit clock gating disable for VLVJesse Barnes1-0/+1
2012-06-18drm/i915: disable RCBP and VDS unit clock gating on SNB and VLVJesse Barnes1-0/+1
2012-06-14drm/i915: PIPE_CONTROL_TLB_INVALIDATEBen Widawsky1-0/+1
2012-06-14drm/i915: Ivybridge MI_ARB_ON_OFF context w/aBen Widawsky1-0/+3
2012-06-14drm/i915: CXT_SIZE register offsets addedBen Widawsky1-0/+21
2012-06-12drm/i915: clear up backlight #define confusion on gen4+Daniel Vetter1-20/+35
2012-06-12drm/i915: pnv has a backlight polarity control bit, tooDaniel Vetter1-0/+2
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-29 16:47:39 +0300