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2022-09-19drm/i915/hotplug: refactor hotplug init slightlyJani Nikula2-6/+18
Rename intel_hpd_init_work() to the more generic intel_hpd_init_early(), and move the hotplug storm initialization there. This lets us move the HPD_STORM_DEFAULT_THRESHOLD macro to intel_hotplug.c too. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220916130634.3781122-2-jani.nikula@intel.com
2022-09-19drm/i915/hotplug: move hotplug storm debugfs to intel_hotplug.cJani Nikula3-158/+169
The debugfs should be where the implementation details are. v2: Rebase Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220916130634.3781122-1-jani.nikula@intel.com
2022-09-15Merge tag 'drm-intel-next-2022-08-29' of ↵Dave Airlie52-568/+2548
git://anongit.freedesktop.org/drm/drm-intel into drm-next drm/i915 feature pull for v6.1: Features and functionality: - Early Meteorlake (MTL) enabling (José, Radhakrishna, Clint, Imre, Vandita, Ville, Jani) - Support more HDMI pixel clock frequencies on DG2 (Clint) - Sanity check PCI BARs (Piotr Piórkowski) - Enable DC5 on DG2 (Anusha) - DG2 DMC firmware version bump to v2.07 (Madhumitha) - New ADL-S PCI ID (José) Refactoring and cleanups: - Add display sub-struct to struct drm_i915_private (Jani) - Add initial runtime info to device info (Jani) - Split out HDCP and backlight registers to separate files (Jani) Fixes: - Skip wm/ddb readout for disabled pipes (Ville) - HDMI port timing quirk for GLK ECS Liva Q2 (Diego Santa Cruz) - Fix bw init null pointer dereference (Łukasz Bartosik) - Disable PPS power hook for DP AUX backlight (Jouni) - Avoid warnings on registering multiple backlight devices (Arun) - Fix dual-link DSI backlight and CABC ports for display 11+ (Jani) - Fix Type-C PHY ownership programming in HDMI legacy mode (Imre) - Fix unclaimed register access while loading PIPEDMC-C/D (Imre) - Bump up CDCLK for DG2 (Stan) - Prune modes that require HDMI 2.1 FRL (Ankit) - Disable FBC when PSR1 is enabled in display 12-13 (Matt) - Fix TGL+ HDMI transcoder clock and DDI BUF disable order (Imre) - Disable PSR before disable pipe (José) - Disable DMC handlers during firmware loading/disabling on display 12+ (Imre) - Disable clock gating for PIPEDMC-A/B as a workaround (Imre) Merges: - Two drm-next backmerges (Rodrigo, Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87k06rfaku.fsf@intel.com
2022-09-15drm/i915: Fix return type of mode_valid function hookNathan Huckleberry1-2/+2
All of the functions used for intel_dvo_dev_ops.mode_valid have a return type of enum drm_mode_status, but the mode_valid field in the struct definition has a return type of int. The mismatched return type breaks forward edge kCFI since the underlying function definitions do not match the function hook definition. The return type of the mode_valid field should be changed from int to enum drm_mode_status. Reported-by: Dan Carpenter <error27@gmail.com> Link: https://github.com/ClangBuiltLinux/linux/issues/1703 Cc: llvm@lists.linux.dev Signed-off-by: Nathan Huckleberry <nhuck@google.com> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220913205531.155046-1-nhuck@google.com
2022-09-15drm/i915/mtl: Update CHICKEN_TRANS* register addressesMadhumitha Tolakanahalli Pradeep2-4/+14
In Display version 14, Transcoder Chicken Registers have updated address. This patch performs checks to use the right register when required. v2: Omit display version check in i915_reg.h(Jani) v3: - Remove extra whitespace introduced - Fix reg definitions for MTL_CHICKEN_TRANS(MattR) Bspec: 34387, 50054 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220913183341.908028-6-radhakrishna.sripada@intel.com
2022-09-15drm/i915/mtl: Update MBUS_DBOX creditsRadhakrishna Sripada1-6/+42
Display version 14 platforms have different credits values compared to ADL-P. Update the credits based on pipe usage. v2: Simplify DBOX BW Credit definition(MattR) v3: - Simplify only pipe per dbuf bank check(MattR) - Skip modeset check to handle the case when a new pipe within dbuf bank gets added/removed.(MattR) Bspec: 49213 Cc: Jose Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Caz Yokoyama Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220913183341.908028-5-radhakrishna.sripada@intel.com
2022-09-14Merge tag 'backlight-detect-refactor-1' of ↵Maxime Ripard4-1/+38
git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86 into drm-misc-next Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86 Tag (immutable branch) with v6.0-rc1 + the (acpi/x86) backlight detect refactor work. For merging into the acpi, drm-* and pdx86 subsystems. Signed-off-by: Maxime Ripard <maxime@cerno.tech> # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEEuvA7XScYQRpenhd+kuxHeUQDJ9wFAmMVsogUHGhkZWdvZWRl # QHJlZGhhdC5jb20ACgkQkuxHeUQDJ9yy6wgAlig+7hkq940L62lTpj0g2gNQv8zc # HCsMpnU7dnJcZYaEvIjouZhf33ZbN52c0fQq2JWjt7fFX04LLyIiyrJ26Lc293JR # ++yXpJcVoewRGqApy/P3Z05TKUCLll5bexvK4t8isnhOtEXD/nDPWKTLIV2Kd1DK # nLY4KgRznXZ85RhYheUEdidZ7Lwlzt1JVBMq7tpnzu3nVdDExyZmqlqCUITcLynu # ysuASQGr0D2i+1vb9eifHIA3xsQO0S37Bv62aBMBKxB6B8Fz1DYr8VA2YvoT82Hv # IFT0hzCCZ/63Ljga05O78TwraxAQX0RvZWqjqGgnZg6fIBh2hxUiqeQY6g== # =SA1R # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 Sep 2022 09:25:44 AM IST # gpg: using RSA key BAF03B5D2718411A5E9E177E92EC4779440327DC # gpg: issuer "hdegoede@redhat.com" # gpg: Can't check signature: No public key From: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/261afe3d-7790-e945-adf6-a2c96c9b1eff@redhat.com
2022-09-14drm/i915/dsc: convert dsc debugfs entry from output_bpp to input_bpcSwati Sharma3-31/+19
Convert dsc debugfs entry from output_bpp to input_bpc. The rationale is to validate different input bpc across various platforms. v2: -improved commit message (Jani N) -styling fixes (Jani N) Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902190658.9459-2-swati2.sharma@intel.com
2022-09-13drm/i915/ipc: use intel_uncore_rmw() to enable/disableJani Nikula1-10/+2
Don't duplicate the rmw function. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/113a17cd18401b0e4c83396575b67aa6efb07346.1662983005.git.jani.nikula@intel.com
2022-09-13drm/i915/display: move IPC under display wm sub-structJani Nikula2-3/+5
Move display IPC related member under drm_i915_private display sub-struct. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/04ccaaceee9293e5a6c75761ba9d36792c36f095.1662983005.git.jani.nikula@intel.com
2022-09-13drm/i915/ipc: register debugfs only if IPC availableJani Nikula1-3/+3
It looks like trying to enable IPC via debugfs on platforms that don't have IPC resulted in dmesg info message about IPC being enabled, which is clearly not possible and would not happen. Seems sensible to register IPC debugfs only on platforms that have IPC. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b18edb4f96c9d2ec728ef04e6f99d161fe5641d1.1662983005.git.jani.nikula@intel.com
2022-09-13drm/i915/ipc: move IPC debugfs to skl_watermark.cJani Nikula3-53/+63
Follow the new direction for debugfs files, moving the details where the implementation is. It seems quite natural skl_watermark.c is the place that controls IPC details, even for debugfs, not intel_display_debugfs.c. Rename the functions and convert dev_priv->i915 while at it. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9d59b18f5dc06e86a48c1ce0f40d625f51e3e85a.1662983005.git.jani.nikula@intel.com
2022-09-13drm/i915/ipc: refactor and rename IPC functionsJani Nikula4-19/+23
Rename the IPC functions to have skl_watermark_ipc_ prefix, rename enable to update to reflect what the function actually does, and add enabled function to abstract direct ->ipc_enabled access for state query. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/536237d5bc919e8c97a96796f235f5bb264ceff2.1662983005.git.jani.nikula@intel.com
2022-09-13drm/i915/display: Use drm helper instead of own loop for damage clipsJouni Högander1-12/+5
Use existing drm_atomic_helper_damage_merged from generic drm code instead of implementing own loop to iterate over damage_clips. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220823112920.352563-4-jouni.hogander@intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2022-09-13drm/i915/display: Use original src in psr2 sel fetch area calculationJouni Högander1-1/+2
drm_plane_state->src is modified when offset is calculated: before calculation: src.x1 = 8192, src.y1 = 8192 after calculation (pitch = 65536, cpp = 4, alignment = 262144) src.x1 = 8192, src.y1 = 0, offset = 0x20000000 Damage clips are relative to original coodrdinates provided by user-space. To compare these against src coordinates we need to use original coordinates as provided by user-space. These can be obtained by using drm_plane_state_src. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220823112920.352563-3-jouni.hogander@intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2022-09-13drm/i915/psr: Disable PSR2 when SDP is sent on prior lineJouni Högander1-1/+2
Selective update doesn't work if SU start address is 0 and start/end SDP is configured to be sent prior to SU start/end lines. PSR2 has to be disabled in this case for Alder Lake. HSDES: 22012279113 Cc: Mika Kahola <mika.kahola@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220905102355.176622-3-jouni.hogander@intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2022-09-13drm/i915/psr: Equation changed for sending start/stop on prior lineJouni Högander1-2/+2
Equation for sending start/end SDP prior to the SU region start/end has changed. Update used formula. Bspec: 49274 Cc: Mika Kahola <mika.kahola@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220905102355.176622-2-jouni.hogander@intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2022-09-13drm/i915: Fix TV encoder clock computationVille Syrjälä2-8/+23
The TV encoder has its own special clocking strategy, which means we can't just use intel_crtc_dotclock() to figure out what the resulting dotclock will be given the actual DPLL port_clock. Additionally the DPLL can't always generate exactly the frequency we initially asked for. This results in us computing a bogus dotclock/etc., and it won't match the readout which is handled by the encoder itself properly. Naturally the state checker becomes unhappy with the mismatch. To do this sanely we'll need to move the DPLL computation into encoder->compute_config() so that all the derived state gets correctly computed based on the actual DPLL output frequency. Start doing that just for the TV encoder initally as intel_crtc_dotclock() should be able to handle other encoder types well enough. Though eventually this should be done for all encoder types rather than doing it from intel_crtc_compute_config(). With this we actually do some of the DPLL state computation twice, but we can skip the second actual .find_dpll() search by flagging .clock_set=true after we've done it once. We also still need to avoid clobbering the correct adjusted_mode.crtc_clock set up by encoder->compute_config() when called a second time from intel_crtc_compute_config(). Fixes: 665a7b04092c ("drm/i915: Feed the DPLL output freq back into crtc_state") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220909205932.32537-1-ville.syrjala@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com>
2022-09-13drm/i915/bios: Add the "Disable compression for the Display Port/HDMI ↵Ville Syrjälä1-1/+2
external display" bit The child device block has gained a new bit for disabling compression for external displays. Seems stupid, but there it is. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907093534.29004-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-09-13drm/i915/bios: Fix VBT ACPI DPMS bit polarityVille Syrjälä1-1/+1
We have the ACPI vs. not ACPI DPMS bit polarity the wrong way around. Fix it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907093534.29004-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-09-13drm/i915/dp: use drm_dp_phy_name() for loggingJani Nikula1-47/+36
Drop the local intel_dp_phy_name() function, and replace with drm_dp_phy_name(). This lets us drop a number of local buffers. v2: Rebase Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220912132313.2774603-1-jani.nikula@intel.com
2022-09-13drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailboxRadhakrishna Sripada2-6/+44
From Meteorlake, Latency Level, SAGV bloack time are read from LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type and QGV information are also to be read from Mem SS registers. v2: - Simplify MTL_MEM_SS_INFO_QGV_POINT macro(MattR) - Nit: Rearrange the bit def's from higher to lower(MattR) - Restore platform definition for ADL-P(MattR) - Move back intel_qgv_point def to intel_bw.c(Jani) v3: - Rebase Bspec: 64636, 64608 Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Original Author: Caz Yokoyama Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902060342.151824-9-radhakrishna.sripada@intel.com
2022-09-13drm/i915/mtl: Add DP AUX support on TypeC portsImre Deak1-1/+44
On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have changed wrt. previous platforms, adjust the code accordingly. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902060342.151824-8-radhakrishna.sripada@intel.com
2022-09-13drm/i915/mtl: Add display power wellsImre Deak4-1/+170
Add support for display power wells on MTL. The differences from XE_LPD: - The AUX HW block is moved to the PICA block, where the registers are on an always-on power well and the functionality needs to be powered on/off via the AUX_CH_CTL register: [1], [2] - The DDI IO power on/off programming sequence is moved to the PHY PLL enable/disable sequence. [3], [4], [5] Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450 v2: - Update the comment in aux power well enable - Reuse the noop sync fn for aux sync. - Use REG_BIT for new register bit definitions Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902060342.151824-7-radhakrishna.sripada@intel.com
2022-09-13drm/i915/mtl: Add gmbus and gpio supportRadhakrishna Sripada2-0/+16
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. From spec we have registers GPIO_CTL[1-5] mapped to native display phys and GPIO_CTL[9-12] are mapped to TC ports. v2: - Drop unused GPIO pins(MattR) BSpec: 49306 Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Brian J Lovin Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902060342.151824-6-radhakrishna.sripada@intel.com
2022-09-12Merge tag 'drm-intel-gt-next-2022-09-09' of ↵Dave Airlie7-18/+18
git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709" The intent of Wa_14015141709 was to inform us that userspace can no longer control object-level preemption as it has on past platforms (i.e., by twiddling register bit CS_CHICKEN1[0]). The description of the workaround in the spec wasn't terribly well-written, and when we requested clarification from the hardware teams we were told that on the kernel side we should also probably stop setting FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the hardware to honor the settings in per-context register CS_CHICKEN1. It turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a mistake; even though CS_CHICKEN1[0] is non-operational and useless to userspace, there are other bits in the register that do still work and might need to be adjusted by userspace in the future (e.g., to implement other workarounds that show up). If we don't set FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would not take effect. Even more details at: https://lists.freedesktop.org/archives/intel-gfx/2022-September/305478.html Driver Changes: - Align GuC/HuC firmware versioning scheme to kernel practices (John) - Fix #6639: h264 hardware video decoding broken in 5.19 on Intel(R) Celeron(R) N3060 (Nirmoy) - Meteorlake (MTL) enabling (Matt R) - GuC SLPC improvements (Vinay, Rodrigo) - Add thread execution tuning setting for ATS-M (Matt R) - Don't start PXP without mei_pxp bind (Juston) - Remove leftover verbose debug logging from GuC error capture (John) - Abort suspend on low system memory conditions (Nirmoy, Matt A, Chris) - Add DG2 Wa_16014892111 (Matt R) - Rename ggtt_view as gtt_view (Niranjana) - Consider HAS_FLAT_CCS() in needs_ccs_pages (Matt A) - Don't try to disable host RPS when this was never enabled. (Rodrigo) - Clear stalled GuC CT request after a reset (Daniele) - Remove runtime info printing from GuC time stamp logging (Jani) - Skip Bit12 fw domain reset for gen12+ (Sushma, Radhakrishna) - Make GuC log sizes runtime configurable (John) - Selftest improvements (Daniele, Matt B, Andrzej) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/YxshfqUN+vDe92Zn@jlahtine-mobl.ger.corp.intel.com
2022-09-12Merge drm/drm-next into drm-intel-nextJani Nikula12-84/+95
Backmerge to sync the DP MST atomic changes to drm-intel-next. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2022-09-11Merge tag 'drm-misc-next-2022-09-09' of ↵Dave Airlie4-64/+72
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v6.1-rc1: [airlied - fix sun4i_tv build] UAPI Changes: - Hide unregistered connectors from GETCONNECTOR ioctl. - drm/virtio no longer advertises LINEAR modifier, as it doesn't work. - Cross-subsystem Changes: - Fix GPF in udmabuf failure path. Core Changes: - Rework TTM placement to use intersect/compatible functions. - Drop legacy DP-MST support. - More DP-MST related fixes, and move all state into atomic. - Make DRM_MIPI_DBI select DRM_KMS_HELPER. - Add audio_infoframe packing for DP. - Add logging when some atomic check functions fail. - Assorted documentation updates and fixes. Driver Changes: - Assorted cleanups and fixes in msm, lcdif, nouveau, virtio, panel/ilitek, bridge/icn6211, tve200, gma500, bridge/*, panfrost, via, bochs, qxl, sun4i. - Add add AUO B133UAN02.1, IVO M133NW4J-R3, Innolux N120ACA-EA1 eDP panels. - Improve DP-MST modeset state handling in amdgpu, nouveau, i915. - Drop DP-MST from radeon driver, it was broken and only user of legacy DP-MST. - Handle unplugging better in vc4. - Simplify drm cmdparser tests. - Add DP support to ti-sn65dsi86. - Add MT8195 DP support to mediatek. - Support RGB565, XRGB64, and ARGB64 formats in vkms. - Convert sun4i tv support to atomic. - Refactor vc4/vec TV Modesetting, and fix timings. - Use atomic helpers instead of simple display helpers in ssd130x. Maintainer changes: - Add Douglas Anderson as reviewer for panel-edp. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a489485b-3ebc-c734-0f80-aed963d89efe@linux.intel.com
2022-09-09drm/i915: Use REG_FIELD_GET() to extract skl+ wm latenciesVille Syrjälä1-14/+8
Replace the hand rolled stuff with REG_FIELD_GET() for reading out the skl+ watermark latencies. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220908191646.20239-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-09-09drm/i915: Extract skl_watermark.cVille Syrjälä12-7/+3560
Pull all the skl+ watermark code (and the dbuf/sagv/ipc code since it's all sort of intertwined and I'm too lazy to think of a finer grained split right now) into its own file from the catch-all intel_pm.c. Also sneak in the s/dev_priv/i915/ rename while at it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220908191646.20239-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-09-09drm/i915/dsb: hide struct intel_dsb betterJani Nikula4-28/+32
struct intel_dsb can be an opaque type, hidden in intel_dsb.c. Make it so. Reduce related includes while at it. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220908165702.973854-1-jani.nikula@intel.com
2022-09-08drm/i915: Round TMDS clock to nearestVille Syrjälä2-2/+3
Use round-to-nearest behavour when calculating the TMDS clock. Matches what we do for most other clock related things. Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-18-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Use a fixed N value alwaysVille Syrjälä5-30/+25
Windows/BIOS always uses fixed N values. Let's match that behaviour. Allows us to also get rid of that constant_n quirk stuff. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-17-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Allow M/N change during fastset on bdw+Ville Syrjälä3-8/+43
On BDW+ M/N are double buffered and so we can easily reprogram them during a fastset. So for eDP panels that support seamless DRRS we can just change these without a full modeset. For earlier platforms we'd need to play tricks with M1/N1 vs. M2/N2 during the fastset to make sure we do the switch atomically. Not sure the added complexity is worth the hassle, so leave it alone for now. The slight downside is that we have to keep the link running at a link rate capable of supporting the highest refresh rate we want to use. For the moment we just pick the highest mode the panel reports and calculate the link based on that. This might need further refinement (eg. if we run into bandwidth restrictions)... v2: Only use the high link rate if the platform really supports the seamless M/N change uring fastset (ie. bdw+) v3: Rebase due to HAS_DOUBLE_BUFFERED_M_N() Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-16-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Add intel_panel_highest_mode()Ville Syrjälä2-0/+18
Add a function to get the fixed_mode with the highest clock. The plan is to use this for the link bw calculation on seamless DRRS panels so that we alwasy end up with the same link params regardless of the requested refresh rate. This will allow fastset to do seamless refresh rate changes based on userspace request instead of having to go for a full modeset. TODO: the function name isn't great Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-15-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabledVille Syrjälä1-3/+5
No sense in calling intel_modeset_pipe_config_late() for a disabled pipe. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-14-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Nuke fastet state copy hacksVille Syrjälä1-25/+3
Now that we no longer do the fuzzy clock and M/N checks we can get rid of the fastset state copy hacks. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-13-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Set active dpll early for icl+Ville Syrjälä1-0/+6
To make the fastboot checks at least somewhat sensible let's mark the expected DPLL as the active one right after we finished the state computation. Otherwise intel_pipe_config_compare() will always be comparing things against NULL/0. TODO: This is still not really right. If the previous commit had to fall back to the other PLL then the comparisong will now fail. I guess intel_pipe_config_compare() should rather be comparing port_dplls[] instead. But to do that we really should just unify every platform to use the port_dplls[] approach whether they have any need for PLL fallbacks or not. Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-12-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Make all clock checks non-fuzzyVille Syrjälä1-15/+4
Now that we backfeed the actual DPLL frequency into the compute crtc state all our clocks should come out exact. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-11-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Make M/N checks non-fuzzyVille Syrjälä2-45/+13
Now that we no longer fuzz M/N during fastset these should match exctly. In order to get a match with what the BIOS does we need to round M/N down. And we do the opposite rounding when doing the readback. That gets us pretty much the same thing back. There can still be slight rounding differences between FDI M/N vs. the DPLL output so we allow for tiny deviation in intel_pipe_config_sanity_check(). v2: Tweak rounding/sanity check stuff a bit Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-10-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Compute clocks earlierVille Syrjälä1-4/+4
Do the DPLL computation before fastset checks. This should allow us to get rid of all that horrible fuzzy clock handling for fastsets. Who knows how many bugs there are caused by our state not actually matching what the hardware will generate. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-9-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä7-12/+117
Fill port_clock and hw.adjusted_mode.crtc_clock with the actual frequency we're going to be getting from the hardware. This will let us accurately compute all derived state that depends on those. v2: Reintroduce iCLKIP WARN v3: Try to deal with VLV/BXT DSI PLL as well Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-8-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()Ville Syrjälä2-20/+3
Only reassign the pipe's DPLL if it's going through a full .compute_config() cycle. If OTOH it's just getting modeset eg. in order to change cdclk there doesn't seem much point in picking a new DPLL for it. This should also prevent .get_dplls() from seeing a funky port_clock for DP even in cases where the readout produces a non-standard clock and we (for some reason) have decided to not fully recompute the state to remedy the situation. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-7-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Do .crtc_compute_clock() earlierVille Syrjälä2-7/+5
Currently we calculate a lot of things (pixel rate, watermarks, cdclk) trusting that the DPLL can generate the exact frequency we ask it. In practice that is not true and there can be certain amount of rounding involved. To allow us to eventually get accurate numbers for all our DPLL clock derived state we need to move the DPLL calculation to hapen much earlier. To that end we hoist it up to the just after the fastset checks. For now we just do the easy code motion, and the actual back feeding of the final DPLL clock into the state will come later. A slight change here is that now .crtc_compute_clock() can get called while the shared_dpll is still assigned. But since .crtc_compute_clock() no longer assignes new shared_dplls this is perfectly fine. TODO: I'd actually like to do this before the fastset check so that if the DPLL state should change we actually do the modeset. Which I think is what the video aficionados want, but it might not be what the fans of fastboot want. Not yet sure how to reconcile those conflicting requirements... v2: s/return/goto/ in error handling Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-6-ville.syrjala@linux.intel.com
2022-09-08drm/i915: Rename ggtt_view as gtt_viewNiranjana Vishwanathapura7-18/+18
So far, different views (normal, partial, rotated and remapped) into the same object are only supported for GGTT mappings. But with the upcoming VM_BIND feature, PPGTT will also use the partial view mapping. Hence rename ggtt_view to more generic gtt_view. Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220901183854.3446-1-niranjana.vishwanathapura@intel.com
2022-09-08drm/i915/vdsc: Set VDSC PIC_HEIGHT before using for DP DSCAnkit Nautiyal3-1/+3
Currently, pic_height of vdsc_cfg structure is being used to calculate slice_height, before it is set for DP. So taking out the lines to set pic_height from the helper intel_dp_dsc_compute_params() to individual encoders, and setting pic_height, before it is used to calculate slice_height for DP. Fixes: 5a6d866f8e1b ("drm/i915: Get slice height before computing rc params") Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902103219.1168781-1-ankit.k.nautiyal@intel.com
2022-09-07drm/i915/dsi: Extract {vlv,bxt}_get_pclk()Ville Syrjälä1-53/+68
Extract the state->freq computation for VLV/BXT DSI PLL into small helpers. We want to use these during the state computation as well. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-5-ville.syrjala@linux.intel.com
2022-09-07drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N()Ville Syrjälä2-3/+2
We have a couple of places that want to make distinction between double buffered M/N registers vs. the split M1/N1+M2/N2 registers. Add a helper for that. v2: Turn into a HAS_ macro (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-4-ville.syrjala@linux.intel.com
2022-09-07drm/i915: Shuffle some PLL code aroundVille Syrjälä1-85/+85
Shuffle some PLL functions around a bit to avoid ugle forward declarations later on. No functional changes. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-3-ville.syrjala@linux.intel.com
2022-09-07drm/i915: Relocate intel_crtc_dotclock()Ville Syrjälä2-22/+22
intel_crtc_dotclock() is a bit misplaced. In lieu of a better place let's just move it next to its friends in intel_display.c. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-2-ville.syrjala@linux.intel.com
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 20:04:21 +0300