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path: root/drivers/gpu/drm/i915/display/intel_cdclk.c
AgeCommit message (Expand)AuthorFilesLines
2020-01-31drm/i915: Convert cdclk to global stateVille Syrjälä1-83/+109
2020-01-31drm/i915: Introduce better global state handlingVille Syrjälä1-4/+4
2020-01-31drm/i915: s/init_cdclk/init_cdclk_hw/Ville Syrjälä1-12/+12
2020-01-31drm/i915: swap() the entire cdclk stateVille Syrjälä1-15/+3
2020-01-31drm/i915: Extract intel_cdclk_stateVille Syrjälä1-77/+91
2020-01-31drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling conventionVille Syrjälä1-22/+22
2020-01-31drm/i915: s/cdclk_state/cdclk_config/Ville Syrjälä1-211/+215
2020-01-31drm/i915: s/need_cd2x_updare/can_cd2x_update/Ville Syrjälä1-7/+7
2020-01-31drm/i915: Collect more cdclk state under the same roofVille Syrjälä1-14/+26
2020-01-31drm/i915: Move more cdclk state handling into the cdclk codeVille Syrjälä1-6/+20
2020-01-27drm/i915/cdclk: use intel_de_*() functions for register accessJani Nikula1-65/+68
2020-01-23drm/i915/cdclk: use new struct drm_device logging macrosWambui Karuga1-45/+64
2020-01-13drm/i915: Bump up CDCLK to eliminate underruns on TGLStanislav Lisovskiy1-0/+12
2019-11-19drm/i915/ehl: Update voltage level checksMatt Roper1-1/+3
2019-11-01drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.Maarten Lankhorst1-6/+6
2019-11-01drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.Maarten Lankhorst1-4/+4
2019-10-24drm/i915: Allow planes to declare their minimum acceptable cdclkVille Syrjälä1-0/+16
2019-10-24drm/i915: Rework global state lockingVille Syrjälä1-43/+59
2019-10-24drm/i915: Add debugs to distingiush a cd2x update from a full cdclk pll updateVille Syrjälä1-0/+5
2019-10-15drm/i915: Make .modeset_calc_cdclk() mandatoryVille Syrjälä1-6/+25
2019-09-16drm/i915: Extract intel_modeset_calc_cdclk()Ville Syrjälä1-5/+130
2019-09-12drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcsVille Syrjälä1-37/+9
2019-09-12drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+Ville Syrjälä1-35/+2
2019-09-12drm/i915: Fix CD2X pipe select masking during cdclk sanitationVille Syrjälä1-19/+23
2019-09-12drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glkVille Syrjälä1-1/+2
2019-09-11drm/i915/display: Add glk_cdclk_tableChris Wilson1-1/+4
2019-09-11drm/i915: Consolidate {bxt,cnl,icl}_init_cdclkMatt Roper1-63/+2
2019-09-11drm/i915: Enhance cdclk sanitizationMatt Roper1-2/+32
2019-09-11drm/i915: Add calc_voltage_level display vfuncMatt Roper1-49/+26
2019-09-11drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclkMatt Roper1-34/+14
2019-09-11drm/i915: Kill cnl_sanitize_cdclk()Matt Roper1-44/+2
2019-09-11drm/i915: Combine bxt_set_cdclk and cnl_set_cdclkMatt Roper1-148/+119
2019-09-11drm/i915: Use literal representation of cdclk tablesMatt Roper1-203/+100
2019-09-11drm/i915: Consolidate bxt/cnl/icl cdclk readoutMatt Roper1-187/+138
2019-09-06drm/i915/tgl: Use refclk/2 as bypass frequencyMatt Roper1-2/+5
2019-08-31drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+Matt Roper1-2/+6
2019-08-31drm/i915: Allow /2 CD2X divider on gen11+Matt Roper1-55/+35
2019-08-23drm/i915: Use enum pipe instead of crtc index to track active pipesVille Syrjälä1-6/+6
2019-08-17drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio1-14/+6
2019-08-07drm/i915: rename intel_drv.h to display/intel_display_types.hJani Nikula1-1/+1
2019-07-18drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHVVille Syrjälä1-0/+11
2019-07-11drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()Ville Syrjälä1-6/+6
2019-06-26drm/i915/ehl: Add voltage level requirement tableJosé Roberto de Souza1-12/+23
2019-06-26drm/i915/ehl: Remove unsupported cd clocksJosé Roberto de Souza1-1/+6
2019-06-26drm/i915/icl: Add new supported CD clocksJosé Roberto de Souza1-9/+21
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula1-0/+2853
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