starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-09-11	drm/i915: Enhance cdclk sanitization	Matt Roper	1	-2/+32
2019-09-11	drm/i915: Add calc_voltage_level display vfunc	Matt Roper	1	-49/+26
2019-09-11	drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk	Matt Roper	1	-34/+14
2019-09-11	drm/i915: Kill cnl_sanitize_cdclk()	Matt Roper	1	-44/+2
2019-09-11	drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk	Matt Roper	1	-148/+119
2019-09-11	drm/i915: Use literal representation of cdclk tables	Matt Roper	1	-203/+100
2019-09-11	drm/i915: Consolidate bxt/cnl/icl cdclk readout	Matt Roper	1	-187/+138
2019-09-06	drm/i915/tgl: Use refclk/2 as bypass frequency	Matt Roper	1	-2/+5
2019-08-31	drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+	Matt Roper	1	-2/+6
2019-08-31	drm/i915: Allow /2 CD2X divider on gen11+	Matt Roper	1	-55/+35
2019-08-23	drm/i915: Use enum pipe instead of crtc index to track active pipes	Ville Syrjälä	1	-6/+6
2019-08-17	drm/i915: Wrappers for display register waits	Daniele Ceraolo Spurio	1	-14/+6
2019-08-07	drm/i915: rename intel_drv.h to display/intel_display_types.h	Jani Nikula	1	-1/+1
2019-07-18	drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV	Ville Syrjälä	1	-0/+11
2019-07-11	drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()	Ville Syrjälä	1	-6/+6
2019-06-26	drm/i915/ehl: Add voltage level requirement table	José Roberto de Souza	1	-12/+23
2019-06-26	drm/i915/ehl: Remove unsupported cd clocks	José Roberto de Souza	1	-1/+6
2019-06-26	drm/i915/icl: Add new supported CD clocks	José Roberto de Souza	1	-9/+21
2019-06-17	drm/i915: move modesetting core code under display/	Jani Nikula	1	-0/+2853