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path: root/drivers/gpu/drm/amd/powerplay
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2018-07-24drm/amd/powerplay: slow UCLK switch when multiple displays not in syncEvan Quan1-1/+2
Slow switch for UCLK when there is multiple displays and they are not in sync. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rex.zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-20drm/amd/pp: Set Max clock level to display by defaultRex Zhu1-2/+7
avoid the error in dmesg: [drm:dm_pp_get_static_clocks] *ERROR* DM_PPLIB: invalid powerlevel state: 0! Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-20drm/amd/pp: Update clk with od setting when set power stateRex Zhu1-0/+15
This can fix the issue resume from S3, the user's OD setting were reverted to default. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-20drm/amd/pp: Read vbios vddc limit before use themRex Zhu1-3/+8
Use the vddc limit before read them from vbios Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-19drm/amd/powerplay: fixed uninitialized valueEvan Quan1-1/+1
The 'result' is not initialized correctly. It causes the API return an error code even on success. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-07-19drm/amdgpu/powerplay: use irq source defines for smu7 sourcesAlex Deucher1-3/+4
Use the newly added irq source defines rather than magic numbers for smu7 thermal interrupts. Rewiewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16Revert "drm/amd/powerplay: fix performance drop on Vega10"Eric Huang1-5/+0
This reverts commit b87079ec7b4d38efee015367315958ce5495ba93. SMU FW team ask to remove this version specific code. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amdgpu/pp: switch smu callback type for get_argument()Alex Deucher7-8/+8
return a uint32_t rather than an int to properly reflect what the function does. Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amdgpu/pp: split out common smumgr smu9 codeAlex Deucher8-354/+242
Split out the shared smumgr code for vega10 and 12 so we don't have duplicate code for both. Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16drm/amdgpu/pp: remove dead vega12 codeAlex Deucher1-29/+0
Commented out. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu/pp/smu7: cache smu firmware tocAlex Deucher2-39/+54
Rather than calculating it everytime we rebuild the toc buffer, calculate it once initially and then just copy the cached results to the vram buffer. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu/pp/smu7: remove local mc_addr variableAlex Deucher1-6/+2
use the structure member directly. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu/pp/smu7: drop unused values in smu data structureAlex Deucher2-4/+1
use kaddr directly rather than secondary variable. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu/pp/smu7: use a local variable for toc indexingAlex Deucher1-11/+12
Rather than using the index variable stored in vram. If the device fails to come back online after a resume cycle, reads from vram will return all 1s which will cause a segfault. Based on a patch from Thomas Martitz <kugel@rockbox.org>. This avoids the segfault, but we still need to sort out why the GPU does not come back online after a resume. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105760 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd: Use newly added interrupt source defs for SOC15.Andrey Grodzovsky1-3/+5
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd: Use newly added interrupt source defs for VI v3.Andrey Grodzovsky1-3/+5
v2: Rebase v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/powerplay: convert the sclk/mclk into Mhz for comparationEvan Quan1-2/+2
Convert the clocks into right Mhz unit. Otherwise, it will miss the equal situation. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/powerplay: no need to mask workable gfxoff feature for vega12Evan Quan1-1/+1
Gfxoff feature for vega12 is workable. So, there is no need to mask it any more. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/powerplay: add vega12 SMU gfxoff support v3Evan Quan2-0/+41
Export apis for enabling/disabling SMU gfxoff support. v2: fit the latest gfxoff support framework v3: add feature_mask control Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang at amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu/pp/smu7: use a local variable for toc indexingAlex Deucher1-11/+12
Rather than using the index variable stored in vram. If the device fails to come back online after a resume cycle, reads from vram will return all 1s which will cause a segfault. Based on a patch from Thomas Martitz <kugel@rockbox.org>. This avoids the segfault, but we still need to sort out why the GPU does not come back online after a resume. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105760 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-07-10drm/amd/pp: fix semicolon.cocci warningskbuild test robot1-1/+1
drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:1209:17-18: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: ea870e44415a ("drm/amd/pp: Export notify_smu_enable_pwe to display") CC: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amd/pp: Send khz clock values to DC for smu7/8Harry Wentland2-7/+7
The previous change wasn't covering smu 7 and 8 and therefore DC was seeing wrong clock values. This fixes an issue where the pipes seem to hang with a 4k DP and 1080p HDMI display. Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined") Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Cc:rex.zhu@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amd/pp: Convert 10KHz to KHz as variable nameRex Zhu2-3/+2
The default clock unit in powerplay is 10KHz. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/pp: Remove the same struct define in powerplayRex Zhu5-25/+25
delete the same struct define in powerplay, share the struct with display. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/pp: Export notify_smu_enable_pwe to displayRex Zhu1-0/+20
Display can notify smu to enable pwe after gpu suspend. It is used in case when display resumes from S3 and wants to start audio driver by enabling pwe Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/pp: Remove duplicate code in vega12_hwmgr.cRex Zhu1-42/+1
use smu_helper function smu_set_watermarks_for_clocks_ranges in vega12_set_watermarks_for_clocks_ranges. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/pp: Refine the interface exported to displayRex Zhu7-11/+13
use void * as function parameter type in order for extension. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/pp: Switch the tolerable latency for displayrex zhu1-1/+1
Select the lowest MCLK frequency that is within the tolerable latency defined in DISPALY Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/pp: Memory Latency is always 25us on Vega10Rex Zhu1-21/+2
For HBM, 25us latency is enough for memory clock switch. Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/pp: Convert clock unit to KHz as definedRex Zhu3-31/+27
Convert clock unit 10KHz to KHz as the data sturct defined. e.g. struct pp_clock_with_latency { uint32_t clocks_in_khz; uint32_t latency_in_us; }; Meanwhile revert the same conversion in display side. Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1Alex Deucher1-1/+1
Should be using PCIELaneLow for the low clock level. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amdgpu/pp: fix copy paste typo in smu7_init_dpm_defaultsAlex Deucher1-1/+1
Should be mclk rather than sclk. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amdgpu/pp: fix endian swapping in atomctrl_get_voltage_rangeAlex Deucher1-4/+4
Need to swap before doing arthimetic on the values. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amdgpu/pp: add missing byte swapping in process_pptables_v1_0.cAlex Deucher1-4/+4
Values need to be swapped on big endian. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: cosmetic fixEvan Quan2-16/+12
Fix coding style and drop unused variable. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: correct vega12 thermal support as trueEvan Quan1-0/+1
Thermal support is enabled on vega12. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: set vega12 pre display configurationsEvan Quan1-0/+41
Set num_displays to 0 and force uclk high as part of the mode set sequence. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: apply clocks adjust rules on power state changeEvan Quan2-0/+164
This add the apply_clocks_adjust_rules callback which is used to validate the clock settings on a power state change. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: correct vega12 max num of dpm levelEvan Quan1-8/+9
Use MAX_NUM_CLOCKS instead of VG12_PSUEDO* macros for the max number of dpm levels. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: drop unnecessary uclk hard min settingEvan Quan1-10/+0
We don't need to set uclk hard min here because this will be set with other clocks on power state change. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: correct smc display config for multi monitorEvan Quan1-1/+2
Need to take into account multi-head with synced displays. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: initialize uvd/vce powergate status v4Evan Quan1-0/+23
On UVD/VCE dpm enabled/disabled, the powergate status will be set as false/true. So that we will not try to ungate/gate them( enable/disable their dpm) again. v2: added check for uvd/vce powergate status before gating v3: fix typo in description v4: warning fix (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: revise clock level setupEvan Quan1-107/+211
Make sure the clock level set only on dpm enabled. Also uvd/vce/soc clock also changed correspondingly. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: retrieve all clock ranges on startupEvan Quan2-16/+61
So that we do not need to use PPSMC_MSG_GetMin/MaxDpmFreq to get the clock ranges on runtime. Since that causes some problems. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: revise default dpm tables setupEvan Quan1-202/+132
Initialize the soft/hard min/max level correctly and handle the dpm disabled situation. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: drop the acg fixEvan Quan1-6/+0
This workaround is not needed any more. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: smc_dpm_info structure changeEvan Quan4-1/+10
A new member Vr2_I2C_address is added. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/powerplay: correct vega12 bootup values settingsEvan Quan4-12/+91
The vbios firmware structure changed between v3_1 and v3_2. So, the code to setup bootup values needs different paths based on header version. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amdgpu: Add gfx_off support in smu through pp_set_powergating_by_smuRex Zhu1-16/+0
we can take gfx off feature as gfx power gate. gfx off feature is also controled by smu. so add gfx_off support in pp_set_powergating_by_smu. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-06drm/amd/pp: Add powergate_gfx backend function on RavenRex Zhu1-0/+1
Raven support gfx off feature instand of gfx powergate, so use smu10_gfx_off_control as the powergate_gfx backend function. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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