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2021-03-05drm/amd/pm: correct gpu metrics related data structures V3Evan Quan1-0/+112
To make sure they are naturally aligned. Also updating the data type for link_speed/width for future PCIE5 support. V2: define new structures with minor version bumped V3: update data type of energy_accumulator as 64bit and drop unnecessary padding members Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-27amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functionsDarren Powell1-0/+4
v3: updated to include new clocks vclk, dclk, od_vddgfx_offset, od_cclk Added forward declaration for function smu_force_smuclk_levels to resolve clash with other commits Resolved context clashes with other commits and v3 updates to patches 0003, 0004 v2: fix errors flagged by checkpatch New Functions smu_bump_power_profile_mode() - changes profile mode assuming calling function already has mutex smu_force_ppclk_levels() - accepts Powerplay enum pp_clock_type to specify clock to change smu_print_ppclk_levels() - accepts Powerplay enum pp_clock_type to request clock levels amdgpu_get_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to request clock levels and allows all the amdgpu_get_pp_dpm_$CLK functions to have a single codepath amdgpu_set_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to set clock levels and allows all the amdgpu_set_pp_dpm_$CLK functions to have a single codepath Modified Functions smu_force_smuclk_levels - changed function name to make clear difference to smu_force_ppclk_levels smu_force_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level - calls smu_force_smuclk_levels smu_print_smuclk_levels - changed function name to make clear difference to smu_print_ppclk_levels smu_print_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level - calls smu_print_smuclk_levels smu_sys_get_gpu_metrics - modifed arg0 to match Powerplay API get_gpu_metrics smu_get_power_profile_mode - modifed arg0 to match Powerplay API get_power_profile_mode smu_set_power_profile_mode - modifed arg0 to match Powerplay API set_power_profile_mode - removed arg lock_needed, mutex always locked, internal functions can call smu_bump if they already hold lock smu_switch_power_profile - now calls smu_bump as already holds mutex lock smu_adjust_power_state_dynamic - now calls smu_bump as already holds mutex lock amdgpu_get_pp_od_clk_voltage - uses smu_print_ppclk_levels amdgpu_{set,get}_pp_dpm_$CLK - replace logic with call helper function amdgpu_{set,get}_pp_dpm_clock() CLK ={sclk, mclk, socclk, fclk, dcefclk, pci, vclkd, dclk} Other Changes added 5 smu Powerplay functions to swsmu_dpm_funcs removed special smu handling in pm functions and called through Powerplay API Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amdgpu: add SMUIO 11.0.6 register headersLikun Gao2-0/+76
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: enable DCSKenneth Feng1-0/+1
Enable DCS V1: Enable Async DCS. V2: Add the ppfeaturemask bit to enable from the modprobe parameter. V3: 1. add the flag to skip APU support. 2. remove the hunk for workload selection since it doesn't impact the function. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdgpu:Add pcie gen5 support in pcie capability.Feifei Xu1-0/+2
Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-14drm/amd/include/renoir_ip_offset: Mark top-level IP_BASE as __maybe_unusedLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:226:29: warning: ‘UVD0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:219:29: warning: ‘USB0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:212:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:205:29: warning: ‘THM_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:198:29: warning: ‘SMUIO_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:191:29: warning: ‘SDMA0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:184:29: warning: ‘PCIE0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:177:29: warning: ‘OSSSYS_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:172:29: warning: ‘DCN_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:165:29: warning: ‘NBIF0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:158:29: warning: ‘MP1_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:151:29: warning: ‘MP0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:144:29: warning: ‘MMHUB_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:137:29: warning: ‘L2IMU0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:130:29: warning: ‘ISP_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:123:29: warning: ‘IOHC0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:116:29: warning: ‘HDP_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:109:29: warning: ‘HDA_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:102:29: warning: ‘GC_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:95:29: warning: ‘FUSE_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:88:29: warning: ‘DPCS_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:81:29: warning: ‘DMU_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:74:29: warning: ‘DIO_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:67:29: warning: ‘DF_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:60:29: warning: ‘DBGU_IO0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:53:29: warning: ‘CLK_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:46:29: warning: ‘ATHUB_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:39:29: warning: ‘ACP_BASE’ defined but not used [-Wunused-const-variable=] Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-14drm/amd/pm: implement processor fine grain feature for vangogh (v3)Huang Rui1-0/+1
This patch is to implement the processor fine grain feature for vangogh. It's similar with gfx clock, the only difference is below: echo "p core_id level value" > pp_od_clk_voltage 1. "p" - set the cclk (processor) frequency 2. "core_id" - 0/1/2/3, represents which cpu core you want to select 2. "level" - 0 or 1, "0" represents the min value, "1" represents the max value 3. "value" - the target value of cclk frequency, it should be limited in the safe range v2: fix some missing changes as Evan's suggestion. v3: add version check and fix the restore. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-14drm/amd/pm: implement the processor clocks which read by metricHuang Rui1-0/+1
The core processor clocks will be stored in smu metric table, then we add this runtime information into amdgpu_pm_info interface. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amd/pm: support overdrive vddgfx offset setting(V2)Evan Quan1-1/+2
This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. For these ASICs, the target voltage calculation can be illustrated by "voltage = voltage calculated from v/f curve + overdrive vddgfx offset". V2: limit the smu_version check for Sienna Cichlid only Here are some sample usages about this new OD setting: 1. Check current vddgfx offset setting by cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 0mV ... ... 2. Set new vddgfx offset by echo "vo 10" > /sys/class/drm/card0/device/pp_od_clk_voltage cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 10mV ... ... 3. Commit the new setting by echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add osssys v4_2 ip headers (v2)Hawking Zhang2-0/+1645
v1: add osssys v4_2 register offset and shift masks header files. vega20 and arcturus will refer to these ip headers. (Hawking) v2: clean up osssys v4_2 registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
2020-12-11drm/amdgpu: new macro for determining 2ND_USB20PORT supportEvan Quan1-0/+1
Used for determining 2ND_USB20PORT support from firmware_capability. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/include/dimgrey_cavefish_ip_offset: Mark top-level IP_BASE as ↵Lee Jones1-1/+1
__maybe_unused Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c:28: drivers/gpu/drm/amd/amdgpu/../include/dimgrey_cavefish_ip_offset.h:151:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=] 151 | static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/dimgrey_cavefish_ip_offset.h:81:29: warning: ‘FUSE_BASE’ defined but not used [-Wunused-const-variable=] 81 | static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/dimgrey_cavefish_ip_offset.h:74:29: warning: ‘DPCS_BASE’ defined but not used [-Wunused-const-variable=] 74 | static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, | ^~~~~~~~~ NB: Snipped lots of these Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Tao Zhou <tao.zhou1@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Jiansong Chen <Jiansong.Chen@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/include/vangogh_ip_offset: Mark top-level IP_BASE as __maybe_unusedLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c:28: drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:210:29: warning: ‘USB_BASE’ defined but not used [-Wunused-const-variable=] 210 | static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:202:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=] 202 | static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:178:29: warning: ‘PCIE0_BASE’ defined but not used [-Wunused-const-variable=] 178 | static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:154:29: warning: ‘MP2_BASE’ defined but not used [-Wunused-const-variable=] 154 | static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } }, | ^~~~~~~~ NB: Snipped lots of these Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Huang Rui <ray.huang@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/include/sienna_cichlid_ip_offset: Mark top-level IP_BASE as ↵Lee Jones1-1/+1
__maybe_unused Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c:28: drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:186:29: warning: ‘USB0_BASE’ defined but not used [-Wunused-const-variable=] 186 | static const struct IP_BASE USB0_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:179:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=] 179 | static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:158:29: warning: ‘SDMA1_BASE’ defined but not used [-Wunused-const-variable=] 158 | static const struct IP_BASE SDMA1_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } }, | ^~~~~~~~~~ NB: Snipped lots of these Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Likun Gao <Likun.Gao@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/include/navi12_ip_offset: Mark top-level IP_BASE as __maybe_unusedLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c:27: drivers/gpu/drm/amd/amdgpu/../include/navi12_ip_offset.h:179:29: warning: ‘USB0_BASE’ defined but not used [-Wunused-const-variable=] 179 | static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi12_ip_offset.h:172:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=] 172 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi12_ip_offset.h:151:29: warning: ‘SDMA_BASE’ defined but not used [-Wunused-const-variable=] 151 | static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, | ^~~~~~~~~ NB: Snipped a few of these Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/include/navi14_ip_offset: Mark top-level IP_BASE as __maybe_unusedLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c:27: drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:179:29: warning: ‘USB0_BASE’ defined but not used [-Wunused-const-variable=] 179 | static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:172:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=] 172 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:151:29: warning: ‘SDMA_BASE’ defined but not used [-Wunused-const-variable=] 151 | static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, | ^~~~~~~~~ NB: Snipped a few of these Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/include/arct_ip_offset: Mark top-level IP_BASE definition as ↵Lee Jones1-2/+2
__maybe_unused Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/arct_reg_init.c:27: drivers/gpu/drm/amd/amdgpu/../include/arct_ip_offset.h:227:29: warning: ‘DBGU_IO_BASE’ defined but not used [-Wunused-const-variable=] 227 | static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } }, | ^~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/arct_ip_offset.h:127:29: warning: ‘PCIE0_BASE’ defined but not used [-Wunused-const-variable=] 127 | static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } }, | ^~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/arct_reg_init.c:27: drivers/gpu/drm/amd/amdgpu/../include/arct_ip_offset.h:63:29: warning: ‘FUSE_BASE’ defined but not used [-Wunused-const-variable=] 63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } }, | ^~~~~~~~~ Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/include/navi10_ip_offset: Mark top-level IP_BASE as __maybe_unusedLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c:27: drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:127:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=] 127 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:109:29: warning: ‘RSMU_BASE’ defined but not used [-Wunused-const-variable=] 109 | static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:61:29: warning: ‘FUSE_BASE’ defined but not used [-Wunused-const-variable=] 61 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } }, | ^~~~~~~~~ Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/include/vega20_ip_offset: Mark top-level IP_BASE definition as ↵Lee Jones1-1/+1
__maybe_unused In file included from drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c:27: drivers/gpu/drm/amd/amdgpu/../include/vega20_ip_offset.h:154:29: warning: ‘XDMA_BASE’ defined but not used [-Wunused-const-variable= 154 | static const struct IP_BASE XDMA_BASE ={ { { { 0x00003400, 0, 0, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vega20_ip_offset.h:63:29: warning: ‘FUSE_BASE’ defined but not used [-Wunused-const-variable=] 63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } }, | ^~~~~~~~~ Fixes the following W=1 kernel build warning(s): Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/display: Add internal display infoYongqiang Sun1-0/+1
[Why & How] Get internal display info from vbios and pass it to dmub fw to determine if multiple display optmization is needed. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-14drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unusedLee Jones1-38/+38
This patch fixes nearly 400 warnings! These structures are too widely used in too many varying configurations to be split-up into different headers or moved into source files. Instead, we'll mark them as __maybe_unused which tells the compiler that we're aware they're being included into source files which do not make use of them - but we've looked into it, and it's okay. Let's tidy-up whilst were here. Just alignment stuff. Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c:27: drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:179:29: warning: ‘USB0_BASE’ defined but not used [-Wunused-const-variable=] 179 | static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:172:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=] 172 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:151:29: warning: ‘SDMA_BASE’ defined but not used [-Wunused-const-variable=] 151 | static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:144:29: warning: ‘PCIE0_BASE’ defined but not used [-Wunused-const-variable=] 144 | static const struct IP_BASE PCIE0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, | ^~~~~~~~~~ NB: Snipped for brevity Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-14drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry (v2)Prike Liang1-0/+1
The new amdgpu_gfx_state_change_set() funtion can support set GFX power change status to D0/D3. v2: squash in warning fix (Alex) Signed-off-by: Prike Liang <Prike.Liang@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amdgpu: Add and use seperate reg headers for dcn302Bhawanpreet Lakha2-0/+78535
Currently we are using dcn3 reg headers for dcn302. The offsets are different between the two so they need seperate headers. Add dcn302 header files and use these instead of dcn3 header Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10Merge tag 'amd-drm-next-5.11-2020-11-05' of ↵Dave Airlie20-3/+269167
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.11-2020-11-05: amdgpu: - Add initial support for Vangogh - Add support for Green Sardine - Add initial support for Dimgrey Cavefish - Scatter/Gather display support for Renoir - Updates for Sienna Cichlid - Updates for Navy Flounder - SMU7 power improvements - Modifier support for gfx9+ - CI BACO fixes - Arcturus SMU fixes - Lots of code cleanups - DC fixes - Kernel doc fixes - Add more GPU HW client information to page fault error logging - MPO clock tuning for RV - FP fixes for DCN3 on ARM and PPC radeon: - Expose voltage via hwmon on Sumo APUs amdkfd: - Fix unique id handling - Misc fixes From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201105222749.201798-1-alexander.deucher@amd.com
2020-11-05drm/amdgpu: Add GFX Fine Grain Clock Gating flagJinzhou.Su1-0/+1
Add AMD_CG_SUPPORT_GFX_FGCG for FGCG Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amdgpu: drop CONFIG_DRM_AMD_DC_DCN3_01 from atomfirmware.hAlex Deucher1-4/+0
Not needed. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-27drm/amdgpu: add vangogh apu flagHuang Rui1-0/+1
This patch is to add vangogh apu flag to support more kickers that belongs vangogh series. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-27drm/amd/pm: correct VR shared rail infoEvan Quan1-1/+3
Add VR shared rail info. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-27drm/amd/pm: add edc leakage controller settingEvan Quan1-0/+16
Enable edc controller table setting. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-23drm/amdgpu: add GC 10.3 NOALLOC registersAlex Deucher3-0/+36
This adds the NOALLOC registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drmLinus Torvalds17-33/+577
Pull drm updates from Dave Airlie: "Not a major amount of change, the i915 trees got split into display and gt trees to better facilitate higher level review, and there's a major refactoring of i915 GEM locking to use more core kernel concepts (like ww-mutexes). msm gets per-process pagetables, older AMD SI cards get DC support, nouveau got a bump in displayport support with common code extraction from i915. Outside of drm this contains a couple of patches for hexint moduleparams which you've acked, and a virtio common code tree that you should also get via it's regular path. New driver: - Cadence MHDP8546 DisplayPort bridge driver core: - cross-driver scatterlist cleanups - devm_drm conversions - remove drm_dev_init - devm_drm_dev_alloc conversion ttm: - lots of refactoring and cleanups bridges: - chained bridge support in more drivers panel: - misc new panels scheduler: - cleanup priority levels displayport: - refactor i915 code into helpers for nouveau i915: - split into display and GT trees - WW locking refactoring in GEM - execbuf2 extension mechanism - syncobj timeline support - GEN 12 HOBL display powersaving - Rocket Lake display additions - Disable FBC on Tigerlake - Tigerlake Type-C + DP improvements - Hotplug interrupt refactoring amdgpu: - Sienna Cichlid updates - Navy Flounder updates - DCE6 (SI) support for DC - Plane rotation enabled - TMZ state info ioctl - PCIe DPC recovery support - DC interrupt handling refactor - OLED panel fixes amdkfd: - add SMI events for thermal throttling - SMI interface events ioctl update - process eviction counters radeon: - move to dma_ for allocations - expose sclk via sysfs msm: - DSI support for sm8150/sm8250 - per-process GPU pagetable support - Displayport support mediatek: - move HDMI phy driver to PHY - convert mtk-dpi to bridge API - disable mt2701 tmds tegra: - bridge support exynos: - misc cleanups vc4: - dual display cleanups ast: - cleanups gma500: - conversion to GPIOd API hisilicon: - misc reworks ingenic: - clock handling and format improvements mcde: - DSI support mgag200: - desktop g200 support mxsfb: - i.MX7 + i.MX8M - alpha plane support panfrost: - devfreq support - amlogic SoC support ps8640: - EDID from eDP retrieval tidss: - AM65xx YUV workaround virtio: - virtio-gpu exported resources rcar-du: - R8A7742, R8A774E1 and R8A77961 support - YUV planar format fixes - non-visible plane handling - VSP device reference count fix - Kconfig fix to avoid displaying disabled options in .config" * tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm: (1494 commits) drm/ingenic: Fix bad revert drm/amdgpu: Fix invalid number of character '{' in amdgpu_acpi_init drm/amdgpu: Remove warning for virtual_display drm/amdgpu: kfd_initialized can be static drm/amd/pm: setup APU dpm clock table in SMU HW initialization drm/amdgpu: prevent spurious warning drm/amdgpu/swsmu: fix ARC build errors drm/amd/display: Fix OPTC_DATA_FORMAT programming drm/amd/display: Don't allow pstate if no support in blank drm/panfrost: increase readl_relaxed_poll_timeout values MAINTAINERS: Update entry for st7703 driver after the rename Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached" drm/amd/display: HDMI remote sink need mode validation for Linux drm/amd/display: Change to correct unit on audio rate drm/amd/display: Avoid set zero in the requested clk drm/amdgpu: align frag_end to covered address space drm/amdgpu: fix NULL pointer dereference for Renoir drm/vmwgfx: fix regression in thp code due to ttm init refactor. drm/amdgpu/swsmu: add interrupt work handler for smu11 parts drm/amdgpu/swsmu: add interrupt work function ...
2020-10-15drm/amdgpu: add missing newline at eofTom Rix1-1/+1
Representative checkpatch.pl warning WARNING: adding a line without newline at end of file 30: FILE: drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h:30: +#endif Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-12drm/amdgpu: initialize IP offset for dimgrey_cavefishTao Zhou1-0/+1049
Add ip offset definition for dimgrey_cavefish and initialize it. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-12Merge tag 'x86_pasid_for_5.10' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 PASID updates from Borislav Petkov: "Initial support for sharing virtual addresses between the CPU and devices which doesn't need pinning of pages for DMA anymore. Add support for the command submission to devices using new x86 instructions like ENQCMD{,S} and MOVDIR64B. In addition, add support for process address space identifiers (PASIDs) which are referenced by those command submission instructions along with the handling of the PASID state on context switch as another extended state. Work by Fenghua Yu, Ashok Raj, Yu-cheng Yu and Dave Jiang" * tag 'x86_pasid_for_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/asm: Add an enqcmds() wrapper for the ENQCMDS instruction x86/asm: Carve out a generic movdir64b() helper for general usage x86/mmu: Allocate/free a PASID x86/cpufeatures: Mark ENQCMD as disabled when configured out mm: Add a pasid member to struct mm_struct x86/msr-index: Define an IA32_PASID MSR x86/fpu/xstate: Add supervisor PASID state for ENQCMD x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Documentation/x86: Add documentation for SVA (Shared Virtual Addressing) iommu/vt-d: Change flags type to unsigned int in binding mm drm, iommu: Change type of pasid to u32
2020-10-07drm/amdgpu: add Green_Sardine APU flagAlex Deucher1-0/+1
Will be used for Green_Sardine which is a new APU. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tablesRoman Li1-1/+61
Required for vangogh. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu: update new memory types in atomfirmware headerHuang Rui1-0/+5
Add new nemory types in atomfirmware header. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu: add vangogh_reg_base_init function for van goghHuang Rui1-0/+1516
This patch adds vangogh_reg_base_init function to init the register base for van gogh. v2: make vangogh_reg_base_init void, align equality sign Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu: add vangogh asic header files (v2)Huang Rui11-0/+266481
This patch is to add vangogh asic header files. v2: squash in updates Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-30drm/amd/amdgpu: Define and implement a function that collects number ofRamesh Errabolu1-0/+12
waves that are in flight. [Why] Allow user to know how many compute units (CU) are in use at any given moment. [How] Read registers of SQ that give number of waves that are in flight of various queues. Use this information to determine number of CU's in use. Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-By: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/powerplay: add one sysfs file to support the feature to modify gfx ↵Xiaojian Du1-0/+1
clock on Raven/Raven2/Picasso APU. This patch is to add one sysfs file -- "pp_od_clk_voltage" for Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10. This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can be used to configure the min value and the max value for gfx clock limited in the safe range. Command guide: echo "s level clock" > pp_od_clk_voltage s - adjust teh sclk level level - 0 or 1, "0" represents the min value, "1" represents the max value clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the OD_RANGE limits. Example: $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-25drm/include: add PP_FEATURE_MASK comments (v3)Ryan Taylor1-0/+28
Documents PP_FEATURE_MASK enum. Provides instructions on how to use ppfeaturemasks. v2: improve enum definitions and add kernel command line parameters to ppfeaturemask instructions v3: fix alignment issues Signed-off-by: Ryan Taylor <ryan.taylor@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-23drm/amdgpu: Add initial kernel documentation for the amd_ip_block_type ↵Ryan Taylor1-25/+62
structure. v3 Added IP block section to amdgpu.rst. Added more documentation to amd_ip_funcs. Created documentation for amd_ip_block_type. v2: Provides a more detailed DOC section on IP blocks v3: Clarifies the IP block list. Adds info on IP block enumeration. Signed-off-by: Ryan Taylor <ryan.taylor@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-23drm/amdgpu: update athub interrupt harvesting handleStanley.Yang1-1/+3
GCEA/MMHUB EA error should not result to DF freeze, this is fixed in next generation, but for some reasons the GCEA/MMHUB EA error will result to DF freeze in previous generation, diver should avoid to indicate GCEA/MMHUB EA error as hw fatal error in kernel message by read GCEA/MMHUB err status registers. Changed from V1: make query_ras_error_status function more general make read mmhub er status register more friendly Changed from V2: move ras error status query function into do_recovery workqueue Changed from V3: remove useless code from V2, print GCEA error status instance number Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-18drm/amdgpu: add VCN 3.0 AV1 registersAlex Deucher1-0/+34
This adds the AV1 registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-18drm/amdgpu: add the GC 10.3 VRS registersAlex Deucher3-0/+56
Add the VRS registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-18drm/amdgpu: add VCN 3.0 AV1 registersAlex Deucher1-0/+34
This adds the AV1 registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-18drm/amdgpu: add the GC 10.3 VRS registersAlex Deucher3-0/+56
Add the VRS registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-18drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700Tom St Denis2-0/+23
This register was requested for umr debugging support. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-17drm, iommu: Change type of pasid to u32Fenghua Yu1-1/+1
PASID is defined as a few different types in iommu including "int", "u32", and "unsigned int". To be consistent and to match with uapi definitions, define PASID and its variations (e.g. max PASID) as "u32". "u32" is also shorter and a little more explicit than "unsigned int". No PASID type change in uapi although it defines PASID as __u64 in some places. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Joerg Roedel <jroedel@suse.de> Link: https://lkml.kernel.org/r/1600187413-163670-2-git-send-email-fenghua.yu@intel.com
generated by cgit v1.2.3 (git 2.39.0) at 2025-05-05 06:13:50 +0300