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2022-02-03amdgpu/pm: Implement new API function "emit" that accepts buffer base and ↵Darren Powell1-0/+1
write offset (v3) Rewrote patchset to order patches as (API, hw impl, usecase) - added API for new power management function emit_clk_levels This function should duplicate the functionality of print_clk_levels, but this solution passes the buffer base and write offset down the stack. - new powerplay function emit_clock_levels, implemented by smu_emit_ppclk_levels() This function parallels the implementation of smu_print_ppclk_levels and calls emit_clk_levels, and allows the returns of errors - new helper function smu_convert_to_smuclk called by smu_print_ppclk_levels and smu_emit_ppclk_levels Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-By: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-26drm/amdgpu: suppress the warning about enum value 'AMD_IP_BLOCK_TYPE_NUM'Evan Quan1-0/+1
Suppress the warning below on building htmldocs: drivers/gpu/drm/amd/include/amd_shared.h:103: warning: Enum value 'AMD_IP_BLOCK_TYPE_NUM' not described in enum 'amd_ip_block_type' Fixes: 6ee27ee27ba8 ("drm/amd/pm: avoid duplicate powergate/ungate setting") Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-15drm/amd/pm: correct the checks for fan attributes supportEvan Quan1-2/+2
On functionality unsupported, -EOPNOTSUPP will be returned. And we rely on that to determine the fan attributes support. Fixes: 79c65f3fcbb128 ("drm/amd/pm: do not expose power implementation details to amdgpu_pm.c") Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-15drm/amd/pm: revise the performance level setting APIsEvan Quan1-2/+0
Avoid cross callings which make lock protection enforcement on amdgpu_dpm_force_performance_level() impossible. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-15drm/amd/pm: do not expose the smu_context structure used internally in powerEvan Quan1-0/+3
This can cover the power implementation details. And as what did for powerplay framework, we hook the smu_context to adev->powerplay.pp_handle. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-15drm/amd/pm: optimize the amdgpu_pm_compute_clocks() implementationsEvan Quan1-1/+1
Drop cross callings and multi-function APIs. Also avoid exposing internal implementations details. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-15drm/amd/pm: create a new holder for those APIs used only by legacy ASICs(si/kv)Evan Quan1-0/+1
Those APIs are used only by legacy ASICs(si/kv). They cannot be shared by other ASICs. So, we create a new holder for them. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-15drm/amd/pm: do not expose implementation details to other blocks out of powerEvan Quan1-0/+4
Those implementation details(whether swsmu supported, some ppt_funcs supported, accessing internal statistics ...)should be kept internally. It's not a good practice and even error prone to expose implementation details. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-16drm/amdgpu: add support for IP discovery gc_info table v2Alex Deucher1-0/+49
Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-16drm/amdgpu: clean up some leftovers from bring upAlex Deucher2-14/+0
Some old registers leftover from pre-silicon. No longer relevant on real hardware. Remove. Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-14drm/amd: Mark IP_BASE definition as __maybe_unusedIsabella Basso2-7/+7
Silences 166 compile-time warnings like: warning: 'UVD0_BASE' defined but not used [-Wunused-const-variable=] 129 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, | ^~~~~~~~~ warning: 'UMC0_BASE' defined but not used [-Wunused-const-variable=] 123 | static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } }, | ^~~~~~~~~ Signed-off-by: Isabella Basso <isabbasso@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-14drm/amd/display: Add feature flags to disable LTTPRAurabindo Pillai1-0/+2
[Why] Allow for disabling non transparent mode of LTTPR for running tests. [How] Add a feature flag and set them during init sequence. The flags are already being used in DC. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-02amdgpu/pm: Create shared array of power profile name stringsDarren Powell1-0/+4
== Description == All the power profile modes use the same strings (or a subset of) Creating a public array of the strings will allow sharing rather than duplicating for each chip First patch only implements change for navi10, followup with other chips == Changes == Create a declaration of the public array in kgd_pp_interface.h Define the public array in amdgpu_pm.c Modify the implementaiton of navi10_get_power_profile_mode to use new array == Test == LOGFILE=pp_profile_strings.test.log AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES="pp_power_profile_mode " for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/pm: Add STB support in sienna_cichlidAndrey Grodzovsky2-0/+19
Add STB implementation for sienna_cichlid Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/pm: avoid duplicate powergate/ungate settingEvan Quan1-1/+2
Just bail out if the target IP block is already in the desired powergate/ungate state. This can avoid some duplicate settings which sometimes may cause unexpected issues. Link: https://lore.kernel.org/all/YV81vidWQLWvATMM@zn.tnic/ Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214921 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215025 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1789 Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Borislav Petkov <bp@suse.de> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-18drm/amdkfd: remove kgd_dev declaration and initializationGraham Sider1-2/+0
Completes removal of kgd_dev. Direct references to amdgpu_device objects should now be used instead. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-18drm/amdkfd: replace kgd_dev in various kfd2kgd funcsGraham Sider1-15/+14
Modified definitions: - program_sh_mem_settings - set_pasid_vmid_mapping - init_interrupts - address_watch_disable - address_watch_execute - wave_control_execute - address_watch_get_offset - get_atc_vmid_pasid_mapping_info - set_scratch_backing_va - set_vm_context_page_table_base - read_vmid_from_vmfault_reg - get_cu_occupancy - program_trap_handler_settings Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-18drm/amdkfd: replace kgd_dev in hqd/mqd kfd2kgd funcsGraham Sider1-12/+13
Modified definitions: - hqd_load - hiq_mqd_load - hqd_sdma_load - hqd_dump - hqd_sdma_dump - hqd_is_occupied - hqd_destroy - hqd_sdma_is_occupied - hqd_sdma_destroy Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-18drm/amdkfd: add amdgpu_device entry to kfd_devGraham Sider1-0/+1
Patch series to remove kgd_dev struct and replace all instances with amdgpu_device objects. amdgpu_device needs to be declared in kgd_kfd_interface.h to be visible to kfd2kgd_calls. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-20drm/amd/display: Disable hdmistream and hdmichar clocksJake Wang2-0/+10
[Why & How] Disable hdmistream and hdmichar root clocks when not being used. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-13drm/amd/display: Enable PSR by default on newer DCNNicholas Kazlauskas1-2/+3
[Why] For optimal power savings on panels that can support it. This was previously left disabled by default because of issues with compositors that do not pageflip and scan out directly to the frontbuffer. For these compositors we now have detection methods that wait for x number of pageflips after a full update - triggered by a buffer or format change typically. This may introduce bugs or new cases not tested by users so this is only currently targeting newer DCN. [How] Add code in DM to set PSR state by default for newer DCN while falling back to the feature mask for older. Add a global debug flag that can be set to disable it for either. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-04drm/amdgpu: add HWID of SDMA instance 2 and 3Guchun Chen1-0/+2
They are missed. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-30drm/amdgpu: add cyan_skillfish asic header filesZhan Liu6-0/+29456
This patch is to add cyan_skillfish asic header files. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Jun Lei <jun.lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-30gpu: amd: replace open-coded offsetof() with builtinArnd Bergmann1-1/+1
The two AMD drivers have their own custom offsetof() implementation that now triggers a warning with recent versions of clang: drivers/gpu/drm/radeon/radeon_atombios.c:133:14: error: performing pointer subtraction with a null pointer has undefined behavior [-Werror,-Wnull-pointer-subtraction] Change all the instances to use the normal offsetof() provided by the kernel that does not have this problem. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-30drm/amd/amdgpu: Add missing mp_11_0_8_sh_mask.h headerTom St Denis1-0/+355
The commit 2766534b766e1b12e0fa0a4e2e26929e808fde71 added the offset header but didn't add the masks. This adds the masks based on what was selected for the offsets. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-28drm/amdgpu: add poison mode query for DF (v2)Tao Zhou2-0/+137
Add ras poison mode query interface for DF. v2: replace RREG32_PCIE with RREG32_SOC15. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-23drm/amd/display: Fix B0 USB-C DP Alt modeLiu, Zhan1-0/+27
[Why] Starting from B0, along with RDPCSTX, RDPCSPIPE registers are also used. [How] Make sure RDPCSPIPE registers are programmed correctly. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Zhan Liu <Zhan.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-01drm/amd/display: Add DP 2.0 BIOS and DMUB SupportFangzhi Zuo1-0/+4
Parse DP2 encoder caps and hpo instance from bios Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-16drm/amd/pm: drop the unnecessary intermediate percent-based transitionEvan Quan1-2/+2
Currently, the readout of fan speed pwm is transited into percent-based and then pwm-based. However, the transition into percent-based is totally unnecessary and make the final output less accurate. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-16drm/amd/pm: correct the fan speed RPM retrievingEvan Quan1-0/+3
The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed RPM. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-16drm/amd/pm: correct the fan speed PWM retrievingEvan Quan2-0/+6
The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed PWM. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-12drm/amdkfd: CWSR with software schedulerMukul Joshi1-0/+3
This patch adds support to program trap handler settings when loading driver with software scheduler (sched_policy=2). Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Suggested-by: Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-06drm/amdgpu: set RAS EEPROM address from VBIOSJohn Clements1-1/+1
update to latest atombios fw table Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-06drm/amd/amdgpu: add regCP_MEx_INT_STAT_DEBUG for Aldebaran debuggingTom St Denis2-0/+58
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amdgpu: add mp 11.0.8 header for cyan_skillfishLang Yu1-0/+352
The cyan_skillfish will use the mp 11.0.8. Signed-off-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amdgpu: dynamic initialize ip offset for cyan_skillfishTao Zhou1-0/+714
Add ip offset definition for cyan_skillfish and initialize it. v2: squash in ip_offset updates (Alex) Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amdgpu: add cyan_skillfish asic typeTao Zhou1-0/+1
Add cyan_skillfish asic family. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-09drm/amd/pm: drop smu_v13_0_1.c|h files for yellow carpXiaomeng Hou2-886/+0
Since there's nothing special in smu implementation for yellow carp, it's better to reuse the common smu_v13_0 interfaces and drop the specific smu_v13_0_1.c|h files. v2: remove the duplicate register offset and shift mask header files as well. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-08drm/amd/display: DMUB Outbound Interrupt Process-X86Chun-Liang Chang1-0/+4
[Why] dmub would notify x86 response time violation by GPINT_DATAOUT [How] 1. Use GPINT_DATAOUT to trigger x86 interrupt 2. Register GPINT_DATAOUT interrupt handler. 3. Trigger ACR while GPINT_DATAOUT occurred. Signed-off-by: Chun-Liang Chang <Chun-Liang.Chang@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-01drm/amdgpu: add license to umc_8_7_0_sh_mask.hAlex Deucher1-0/+21
Was missing. Add it. Fixes: 6b36fa6143f6ca ("drm/amdgpu: add umc v8_7_0 IP headers") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-01drm/amdgpu: rectify line endings in umc v8_7_0 IP headersLukas Bulwahn1-79/+79
Commit 6b36fa6143f6 ("drm/amdgpu: add umc v8_7_0 IP headers") adds the new file ./drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_7_0_sh_mask.h with DOS line endings, which is very uncommon for the kernel repository. Rectify the line endings in this file with dos2unix. Identified by a checkpatch evaluation on the whole kernel repository and spot-checking for really unexpected checkpatch rule violations. Reported-by: Dwaipayan Ray <dwaipayanray1@gmail.com> Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-01drm/amdgpu: Update NV SIMD-per-CU to 2Joseph Greathouse1-1/+1
Navi series GPUs have 2 SIMDs per CU (and then 2 CUs per WGP). The NV enum headers incorrectly listed this as 4, which later meant we were incorrectly reporting the number of SIMDs in the HSA topology. This could cause problems down the line for user-space applications that want to launch a fixed amount of work to each SIMD. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-06-30drm/amd/display: Enabling eDP no power sequencing with DAL feature maskZhan Liu1-4/+6
[Why] Sometimes, DP receiver chip power-controlled externally by an Embedded Controller could be treated and used as eDP, if it drives mobile display. In this case, we shouldn't be doing power-sequencing, hence we can skip waiting for T7-ready and T9-ready." [How] Added a feature mask to enable eDP no power sequencing feature. To enable this, set 0x10 flag in amdgpu.dcfeaturemask on Linux command line. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-16drm/amd/display: Add interface to get Calibrated Avg Level from FIFOWesley Chalmers2-0/+4
[WHY] Hardware has handed down a new sequence requiring the value of this register be read from clk_mgr. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add u64 throttler status field to gpu_metricsGraham Sider1-1/+57
This patch set adds support for a new ASIC independant u64 throttler status field (indep_throttle_status). Piggybacks off the gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to v2_2) to add field. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: add kernel documentation for smu_get_power_limitDarren Powell1-0/+28
added doc tag "amdgpu_pp_power" with description added tags for enums pp_power_limit_level, pp_power_type added tag for function smu_get_power_limit Test: * Temporary insertion into Documentation/gpu/amdgpu.rst ------------START------------ Power Limit ----------- .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :doc: amdgpu_pp_power .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_limit_level .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_type .. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c :identifiers: smu_get_power_limit -------------END------------- Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: modify Powerplay API get_power_limit to use new pp_power enumsDarren Powell1-2/+3
updated {amd_pm_funcs}->get_power_limit() signature rewrote pp_get_power_limit to use new enums pp_get_power_limit now returns -EOPNOTSUPP for unknown power limit update calls to {amd_pm_funcs}->get_power_limit() * Test Notes * testing hardware was NAVI10 (tests SMU path) ** needs testing on VANGOGH ** needs testing on SMU < 11 ** ie, one of TOPAZ, FIJI, TONGA, POLARIS10, POLARIS11, POLARIS12, VEGAM, CARRIZO, STONEY, VEGA10, VEGA12,VEGA20, RAVEN, BONAIRE, HAWAII * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: clean up smu_get_power_limit function signatureDarren Powell1-0/+14
add two new powerplay enums (limit_level, type) add enums to smu_get_power_limit signature remove input bitfield stuffing of output variable limit update calls to smu_get_power_limit * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amdgpu: Update atomfirmware for DCN3.1 phy tuning and eDP capsNicholas Kazlauskas1-1/+55
[Why & How] We'll need these in driver for phy tuning in DCN3.1. Multiple eDP support also requires understanding which LCD the backlight curve in atombios is for. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amdgpu: add yellow_carp_reg_base_init function for yellow carp (v2)Alex Deucher1-0/+1366
This patch adds yellow_carp_reg_base_init function to init the register base for yellow carp. v2: squash in updates (Alex) Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-05-04 18:41:50 +0300