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path: root/drivers/gpu/drm/amd/display/dc/dcn20
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2019-06-22drm/amd/display: Make sure line size is not zero in DCN2 line buffer size ↵Nikola Cornij1-4/+13
calculations [why] 'Divide by zero' error happens when line size happens to be zero. [how] The code that makes sure line size minimum value can be 1 was already present in DCN1 part of the driver, this is mearly a port to DCN2. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Change DCN2 vupdate start programmingEryk Brol1-6/+3
[Why] In order to ensure that incoming flips are latched and complete immediately, we need to program the vupdate interrupt to come during the back porch of each frame. [How] Program the vupdate start_line to be in the back porch like it's done for DCN1. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Refactor program watermark.Yongqiang Sun2-1/+5
Refactor programming watermark function: Divided into urgent watermark, stutter watermark and pstate watermark. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: fix dcn2 mpc split decisionDmytro Laktyushkin1-1/+1
The split condition is broken and will always activate at the moment. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add hubp_init entry to hubp vtableCharlene Liu3-3/+9
Different HW will need to init HUBP differently. For now, add a vtable entry, and hook a NO-OP for DCN1 and DCN2. In addition, future HW will need to access the HUBPREQ_DEBUG and CUR_TTU_CNTL0 register for hubp_init. Add that here. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Fix ODM combine data formatIlya Bakoulin3-4/+17
[Why] OPTC data format was left at its default value (444) when enabling ODM combine. This caused issues with FPGA capture. [How] Write the OPTC_DATA_FORMAT field when enabling ODM combine. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Remove duplicate define of TO_DCN20_HUBBUBYongqiang Sun1-3/+0
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: enable abm on dcn2Josip Pavic1-7/+7
[Why] ABM is currently not enabled on DCN2. [How] Update the register name list for DCN2 and un-comment the code that creates the abm object. Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Acquire DSC HW resource only if required by streamNikola Cornij2-61/+80
[why] There are ASICs that have fewer DSC engines than pipes, which makes DSC a resource that should be used only if required. [how] Acquire DSC HW resource if required by stream and release when not required anymore. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Disable display writeback on Linux for NV10hersen wu1-1/+1
[WHY] system crash when initialize dwb current linux driver does not support dwb. disable this feature for now. [HOW] set num_dwb = 0 to disable dwb for now Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Mark DSC resource as unused after copying to the secondary ↵Nikola Cornij1-0/+3
ODM pipe [why] DSC resource has to be acquired before it can be used and simply copying a reference to it is very likely to cause problems when accessing DSC. [how] Set DSC resource pointer to NULL to mark it as unused after primary pipe resources were copied to the secondary ODM pipe. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: add global master update lock for DCN2Wenjing Liu3-1/+69
[why] when an update programming sequence requires both front end and back end pipe to be updated synchronously, a global update lock needs to be set to ensure that we don't get a frame with only front end update but not the back end update. [how] setup global lock parameters on enable_stream_timing. enable global lock when pipe_control_lock_global is called. disable global lock when pipe_control_lock is called. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Remove REFCYC regsYongqiang Sun1-5/+2
[Why] Some register fields are not needed. [How] remove them Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add profiling tools for bandwidth validationJoshua Aberback1-0/+13
[Why] We used this change to investigate the performance of bandwidth validation, it will be useful to have if we need to investigate further. [How] We use performance counter tick numbers to profile performance, they live at dc->debug.bw_val_profile (set .enable in debugger to turn on measuring). Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Optimize bandwidth validation by adding early returnJoshua Aberback2-11/+27
We can split validation into three parts: getting voltage level, getting watermarks, and rq/dlg calculations. The voltage level is enough to answer the question "do we support this state", and the rest of it is to determine what hardware programming is needed to support the state. Most of the calls to validate_bandwidth only care about the first part, so we added an early return in that case Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: fix can not turn on two displays due to DSC_RESOURCE failed.Charlene Liu1-0/+6
[Why] Can not turn on two displays at the same time with the asic having only one DSC. DC_DSC_RESOURCE allocation failed. [Solution] Only add_dsc if the timing is dsc capable based on diag_dc and num_dsc Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Fix DCFCLK and SOCCLK not setIlya Bakoulin1-0/+4
[Why] If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML calculations, which ended up causing an assert. [How] Initialize dcfclk_mhz and socclk_mhz values according to the voltage level. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: DCN2 reg refactorsYongqiang Sun2-7/+42
Added some regs and exposed some functions for future use Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: isolate global double buffer lock programmingWenjing Liu3-51/+33
[why] Global optic double buffer lock is currently disabled due to incorrect programming sequence that affects non global lock. [how] Isolate global lock programming sequence out of non global lock programming sequence, so it can be enabled without affecting non global lock. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: move dsc clock from plane_resource to stream_resourceTony Cheng1-1/+1
code restructure. Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Remove dependency on pipe->plane for immedaite flip statusJoshua Aberback2-5/+7
[Why] dcn20_apply_ctx_for_surface can be called with 0 planes, which means we should blank the display. In this case when we get down to dcn20_setup_gsl_group_as_lock, pipe_ctx->plane_state is NULL, but we don't check for it. However, this function is only called by dcn20_pipe_control_lock, and in that function we alraedy have a local for the immediate flip status, which is what we care about in the plane state. [How] - pass in immediate flip status as parameter Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: fix dsc validationDmytro Laktyushkin4-40/+59
Currently dsc is validated not taking the image width limitation into mind. This change addresses that, but due to previous design being limited to non odm dsc validation additional sequence changes are made. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Properly set u clockAidan Wood1-1/+1
[Why] u clk set request was being sent in units of mts, when it needed to be in units of Mhz [How] add a division by 16 to convert from mts to Mhz Signed-off-by: Aidan Wood <Aidan.Wood@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Properly set DCF clockAidan Wood1-2/+5
[Why] If num_states == 0 we did update_bound_box which doesn't updated any max clocks if num_states == 0, therefore we need to do cap_soc_clocks instead, also SMU cannot set DCF clock to a higher than or equal to freq than SOC clock [How] Add a num_states != 0 check for update_bounding_box to be run, and after we run get_maximum_sustainable_clocks we now check if the reported max value of DCF is higher than SOC and if necessary set it to 1000 (becomes 1 after division by 1000) lower than SOC Signed-off-by: Aidan Wood <Aidan.Wood@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Calculate link bandwidth in a common functionNikola Cornij1-1/+2
[why] Currently link bandwidth is calculated in various places using the same multi-step formula. Doing this in one common place makes sure the same formula will indeed be applied to all link bandwidth calculations. It also makes it possible to apply link-setting-specific adjustments that affect effective link bandwidth. [how] Replace all implementations of link bandwidth calculation with a call to a function. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: clean up validation failure log spamDmytro Laktyushkin1-0/+3
Currently dcn2+ validation will unconditionally print a failure reason before validation completes. This change categorizes the failure reason as a warning log and only prints at the end of validation resolving false positives. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: fixed DCC corruptionBob Yang1-2/+2
[Description] swath_bytes_horz_wc should be 256/64/64 for 2160p 32bpp surface Signed-off-by: Bob Yang <Bob.Yang@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()Leo Li1-29/+17
[Why] dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra lock unnecessary. In addition - during full plane updates - all necessary pipes should be locked/unlocked together when modifying hubp to avoid tearing in pipesplit setups. [How] Remove redundant locks, and add function to lock all pipes. If an interdependent pipe update is required, lock down all pipes. Otherwise, lock only the top pipe for the updated pipe tree. Signed-off-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Disconnect DCN2 mpcc when changing tgLeo Li1-3/+4
A previous fix was done for DCN1 that needed to be ported to DCN2: commit 60c677534e73 ("drm/amd/display: Disconnect mpcc when changing tg") Signed-off-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: navi10 bring up skip dsc encoder confighersen wu1-0/+8
not needed for bring up. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: skip dsc config for navi10 bring uphersen wu2-1/+10
[why] we meet a bug when program dsc register even dsc mode is not enabled. disable dsc config for now. we will re-visit this issue. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Refactor DIO stream encoderEric Bernstein2-5/+14
* Pull duplicate audio_clock_info struct to stream_encoder.h * Generalize sec_gsp7* to sec_gsp_pps* * Expose enc1 and enc2 stream encoder audio funcs Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: do not power on eDP power rail earlyAnthony Koo1-3/+0
[Why] Modern Standby may toggle display adapter state between D0 and D3 state unpredictably. But events that cause transition to D0 are not always resulting in a display light up scenario. Modern eDP panels should be able to power on panel logic quickly upon VDD going high. Based on spec, the T3 time between VDD on and HPD high can be between 0 and 80 ms. Doing any tricky sorts of optimization by powering on panel VDD early during D0 transition on can negatively impact other features due to unnecessary power drain and toggling when final system state does not intend for the panel to be lit up. We need OEMs to source higher end panels that have T3 time close to 0 if they want quick S3/Modern Standby resume times. [How] Remove panel VDD power on in init_hw Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: update calculated bounding box logic for NVJun Lei1-31/+24
[why] Current calculation of bounding box will cause DML to increase voltage state due to DPP or DISPCLK, this is unnecessary since from DML perspective we can max DPP/DISP can be supported at DPM0. This is because increasing voltage for DPP/DISP is done separately via actual minimum values of DISP and DPP CLK [how] For each calculated state, DPP, DISP, PHY, and DSC clk should always be set to maximum. FCLK, SOCCLK, and DCFCLK should be based of UCLK. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: disable PSR/ABM before destroy DMCU structPaul Hsieh1-0/+3
[Why] 1. DMCU is not running on some platform but driver still send ABM command. It may cause assert due to DMCU is not alive. 2. To make sure PSR disable when driver disable [How] 1. Add dmcu_is_running in ABM struct, driver can check this flag to determine driver should send ABM command or not. 2. Send PSR disable command when destroy PSR Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Ensure DRR triggers in BPEryk Brol2-2/+36
[Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP. [How] 1. Remove DRR programming during flip 2. Setup manual trigger for DRR event and trigger it after surface programming is complete Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Program VTG params after programming Global Sync for DCN2Joshua Aberback2-0/+7
[Why] VTG has a parameter FP2, which is defined as: if VSTARTUP is before VSYNC: FP2 = number of lines in between VSTARTUP and VSYNC else FP2 = 0 Currently, FP2 is only programmed during "program_timing". However, the position of VSTARTUP is affected by the prefetching requirements on all pipes, so the position might change when we do memory request control on another pipe, so we need to make sure that FP2 stays up-to-date whenever we adjust VSTARTUP. [How] - refactor VTG_CONTROL programming into a new function "set_vtg_params" - call it after calling "program_global_sync" - make sure it's called after because it relies on the cached dlg params Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DSC support for Navi (v2)Harry Wentland10-0/+1777
Add support for DCN2 DSC (Display Stream Compression) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ v2: rebase (Alex) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: update dcn2 dc_plane_capAlex Deucher1-3/+18
To deal with rebasing the code. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: updates for dcn20_update_bandwidthAlex Deucher1-1/+1
Pass extra parameter to validate_bandwidth() callback. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidthAlex Deucher2-2/+4
To deal with changes from rebasing. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 HW Sequencer and ResourceHarry Wentland5-0/+4905
Add DCN2 resource definition and HW Sequencer changes. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 VMIDHarry Wentland2-0/+153
Add support to program DCN2 VMID (Virtual Memory Support) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 DWBHarry Wentland3-0/+1650
Add support to program the DCN2 DWB (Display Writeback) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 MMHUBBUBHarry Wentland2-0/+867
Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 HUBP and HUBBUBHarry Wentland4-0/+1574
Add support to program the DCN2 HUBP (Display to data fabric interface pipe) and HUBBUB (DCN memory HUB interface) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 DPPHarry Wentland3-0/+2181
Add support to program the DCN2 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 MPCHarry Wentland2-0/+811
Add support to program the DCN2 MPC (Multiple pipe and plane combine) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 OPPHarry Wentland2-0/+513
Add support to program the DCN2 OPP (Output Plane Processing) HW Blocks: +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 OPTCHarry Wentland2-0/+518
Add support for programming the DCN2 OPTC (Output Timing Controller) HW Blocks: +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-15 23:34:15 +0300