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path: root/drivers/gpu/drm/amd/display/dc/dcn20
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2020-03-31drm/amd/display: Support P010 pixel formatStylon Wang1-1/+2
[Why] P010 pixel format is not declared as supported in DRM and DM. [How] Add P010 format to the support list presented to DRM and checked in DM Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-19drm/amd/display: add on demand pipe merge logic for dcn2+Dmytro Laktyushkin2-14/+51
Adds logic that will determine if pipes need merging during validation. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-19drm/amd/display: DPP DTO isn't update properly.Yongqiang Sun1-0/+2
[Why] before update dpp DTO, we check dppclks in context to determine it is changed or not, but dppclks in context will be updated anyways after flip is done, so compare dppclks in context will always get an equal result. [How] Add pipe dpp clks in dccg and compare values between dccg and context. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-19drm/amd/display: Remove connect DIG FE to its BE during timing programmingNikola Cornij1-7/+0
[why] Causes regression with MST DSC displays not lighting up after DPMS [how] Revert commit 8cc426d79be1c3 ("drm/amd/display: Program DSC during timing programming") Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-19drm/amd/display: Set disable_dmcu flag properly per asicWyatt Wood1-2/+2
[Why] The default value for disable_dmcu is true, even for asics that require dmcu. [How] Set flag properly per asic. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-19drm/amd/display: fix split threshold w/a to work with mpoDmytro Laktyushkin1-26/+13
Right now only stream count is used to avoid split. This change updates the W/A to check plane count instead. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-19drm/amd/display: workaround for HDMI hotplug in DPMSOFF stateYongqiang Sun1-0/+3
[Why] When hotplug a HDMI monitor during entering S0i3 or DPMSOFF state due to entering infinite loop when calling vbios to program pixel clocks. In this scenario, pll is enabled but phy is not, and there is not a programing guide for this case. [How] Before we having the proper programing guide, before disable pll, doing a phy enable and disable to avoid the issue. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-13drm/amd/display: fix typos for dcn20_funcs and dcn21_funcs structStanley.Yang1-1/+0
In dcn20_funcs and dcn21_funcs struct, the member ".dsc_pg_control = NULL" should be removed due to .dsc_pg_control be assigned to dcn20_dsc_pg_control. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-09drm/amd/display: dcn20: remove an unused functionMelissa Wen1-78/+0
The dpp2_get_optimal_number_of_taps function is never used. Removing just for code cleaning up. Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-09drm/amd/display: Program DSC during timing programmingNikola Cornij1-0/+7
[why] Link or DIG BE can't be exposed to a higher stream bandwidth than they can handle. When DSC is required to fit the stream into the link bandwidth, DSC has to be programmed during timing programming to ensure this. Without it, intermittent issues such as black screen after S3 or a hot-plug can be seen. [how] Move DSC programming from enabling stream on link to timing setup. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-09drm/amd/display: Not check wm and clk change flag in optimized bandwidth.Yongqiang Sun1-16/+10
[Why] System isn't able to enter S0i3 due to not send display count 0 to smu. When dpms off, clk changed flag is cleared alreay, and it is checked when doing optimized bandwidth, and update clocks is bypassed due to the flag is unset. [How] Remove check flag incide the function since watermark values and clocks values are checked during update to determine whether to perform it, no need to check it again outside the function. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-09drm/amd/display: update soc bb for nv14Martin Leung1-0/+114
[why] nv14 previously inherited soc bb from generic dcn 2, did not match watermark values according to memory team [how] add nv14 specific soc bb: copy nv2 generic that it was using from before, but changed num channels to 8 Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05drm/amd/display: Set clock optimization required after update clocksSung Lee1-1/+1
[WHY] We see an issue that caused clk_optimized_required to be set true in certain cases, causing passive flips to fail. This is because of a typo where wm_optimized_required was set twice. [HOW] Set clk_optimized_required to false after updating clocks. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05drm/amd/display: change number of cursor policy for dml calculation.Yongqiang Sun1-5/+10
[Why] vstartup calculation is incorrect due to use 2 number of cursors and result in an underflow when playing video in full screen mode and combines graphic plane and video plane. [How] Apply new policy for dml calculation. 1 cursor for graphic plane, 0 cursor for video plane. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05drm/amd/display: fix image corruption with ODM 2:1 DSC 2 sliceWenjing Liu2-1/+2
[why] When combining two or more pipes in DSC mode, there will always be more than 1 slice per line. In this case, as per DSC rules, the sink device is expecting that the ICH is reset at the end of each slice line (i.e. ICH_RESET_AT_END_OF_LINE must be configured based on the number of slices at the output of ODM). It is recommended that software set ICH_RESET_AT_END_OF_LINE = 0xF for each DSC in the ODM combine. However the current code only set ICH_RESET_AT_END_OF_LINE = 0xF when number of slice per DSC engine is greater than 1 instead of number of slice per output after ODM combine. [how] Add is_odm in dsc config. Set ICH_RESET_AT_END_OF_LINE = 0xF if either is_odm or number of slice per DSC engine is greater than 1. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05drm/amd/display: program DPG_OFFSET_SEGMENT for odm_pipeWenjing Liu3-6/+23
[why] When test pattern is enabled with ODM combine, test pattern is generated by piecing multiple DPGs image together. The current code will program all DPGs with horizontal offset of 0. This will cause all DPGs to output the beginning of the pattern. Instead each DPG should program a horizontal offset of its x position to form a continous pattern when pieced together. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05drm/amd/display: add worst case dcc meta pitch to fake planeJoseph Gravenor2-3/+3
[why] When we have single channel memory, we can not light up 2 4k displays with a 1080p edp, because we don't have enough bw by a small margin. this small margin comes from dcc meta being too large. We however don't have this dcc meta when we create fake planes so, before the flip we will not filter out the mode for 2 4k displays with a 1080p edp [how] Change get_default_swizzle_mode to something more general so we don't end up with a separate function for every missing field in the fake plane. Add a reasonable dcc meta to the fake plane when it is filled in, so we filter out modes that don't have enough bandwidth. To do this, we take the screen width and align it to 1024(8k 60) Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05drm/amd/display: only include FEC overhead if both asic and display support FECWenjing Liu1-0/+1
[why] Some asics don't support FEC but FEC overhead is added into link bandwidth calculation by mistake. This causes certain timing cannot be validated. [how] Only include FEC overhead if both asic and display support FEC. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: limit display clock to 100MHz to avoid FIFO errorYu-ting Shen1-0/+3
[Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Temporarily disable stutter on MPO transitionGeorge Shen1-1/+18
[Why] Underflow sometimes occurs during transition into MPO with stutter enabled. [How] When transitioning into MPO, disable stutter. Re-enable stutter within one frame. Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: optimize prgoram wm and clksYongqiang Sun2-13/+24
[Why] In some display configuration like 1080P monitor playing a 1080P video, if user use ALT+F4 to exit Movie and TV, there is a chance clocks are same only water mark changed. Current clock optimization machanism will result in water mark keeps high after exit Movie and TV app. [How] Return if watermark need to be optimized when doing program watermark, perform the optimization after. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: update dml input population functionDmytro Laktyushkin1-9/+17
Update dcn20_populate_dml_pipes_from_context to correctly handle odm when no surface is provided. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add function pointers for panel related hw functionsAnthony Koo1-0/+2
[Why] Make panel backlight and power on/off functions into hardware specific function pointers [How] Add function pointers for panel related hw functions - is_panel_powered_on - is_panel_backlight_on Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Disable PG on NV12Alvin Lee1-0/+9
[Why] According to HW team, PG is dropped for NV12, but programming the registers will still cause power to be consumed, so don't program for NV12. [How] Set function pointer to NULL if NV12 Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-13drm/amdgpu/display move get_num_odm_splits() into dc_resource.cAlex Deucher2-17/+0
It's used by more than just DCN2.0. Fixes missing symbol when amdgpu is built without DCN support. Reviewed-by: Zhan Liu <zhan.liu@amd.com> Tested-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: add odm split logic to scaling calculationsDmytro Laktyushkin2-18/+23
Currently odm scaling calculations are only done when adding initial odm pipe. Any scaling re-calculations will mess up odm because of this. This change resolves the problem by updating scaling split logic to handle odm. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Update register definesAnthony Koo2-27/+0
[Why] Some register defines are redundant or updated [How] Update register defines Remove some redundant defines Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Sun peng Li <Sunpeng.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: external monitor abm enabled in modern standbyJing Zhou1-0/+4
[why] Resume from modern standby, edp stream disabled but abm keep enabled. External monitor select OTG source 0 which ABM enabled. [how] Disable abm before disable crtc when reset path mode not call core link disable stream. Signed-off-by: Jing Zhou <Jing.Zhou@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: decouple global lock out of pipe control lockWenjing Liu1-27/+0
[why] hwss should not guess what type of pipe lock is needed. The caller of the lock function should know the right type of pipe lock. Decouple the setup of global lock outside of pipe control lock logic. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: add stream_enc_inst for PSP HDCP inst useCharlene Liu1-0/+1
[why] new HW engine mapping requirment use in PSP [how] report stream_enc_inst Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: Fix GSL acquireAric Cyr1-6/+0
[Why] After locking refactor GSL is not acquired properly resulting in immediate flip issues. [How] Do not copy old GSL state anymore since GSL is acquired earlier now. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: Added locking for atomic update stream and update planesAnthony Koo3-64/+43
[Why] Screen flickering when HDR switches between FP16 and ARGB2101010 [How] Moved pipe_control_lock so stream update and plane update occur atomically Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Lucy Li <lucy.li@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: Split program front end part that occur outside lockAnthony Koo3-1/+14
[Why] Eventually want to lock at a higher level in stack. To do this, we need to be able to isolate the parts that need to be done after pipe unlock. [How] Split out programming that is done post unlock. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06drm/amd/display: Do not set optimized_require to false after plane disableSung Lee1-1/+0
[WHY] The optimized_require flag is needed to set watermarks and clocks lower in certain conditions. This flag is set to true and then set to false while programming front end in dcn20. [HOW] Do not set the flag to false while disabling plane. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: skip opp blank or unblank if test pattern enabledWenjing Liu1-0/+3
[why] DPG is used to generate both blank and test automation test pattern. When test automation is running the requested test pattern can be overriden by the blank or unblank call because it is using the same hardware. [how] When test pattern is requested, skip blank or unblank. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Use mdelay to avoid context switchMartin Tsai1-2/+2
[why] The rapid msleep operation causes the white line garbage when DAL check flip pending status in SetVidPnSourceVisibility. To execute this msleep will induce context switch, and longer delay could cause worse garbage situation. [how] To replace msleep with mdelay. Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: make PSR static screen entry within 30 msAnthony Koo1-1/+5
[Why] With different refresh rate panels, the PSR entry/exit time is different since it is dependent on 2 frame entry time today [How] Make static screen num frame entry time to be calculated such that entry time is within 30 ms instead of fixed num frames. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Add default switch case for DCCChris Park1-0/+3
Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Indirect reg read macro with shift and maskNoah Abradjian5-33/+37
[Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to manually shift and mask it to retrieve field data. [How] Create new IX_REG_GET macro that handles shift and mask. Use this for double buffering reads instead of IX_REG_READ. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Double buffer dcn2 Gamut RemapNoah Abradjian3-6/+109
[Why] When rapidly adjusting color temperature, screen tearing was observed. This was due to overwritten values in gamut remap registers. This issue was solved for OCSC and ICSC by alternating between "A" and "B" registers to double buffer the writes. [How] Create new set_gamut_remap and program_gamut_remap for dcn20. Alternate which registers are written to by switching modes each time. Also fixes ICSC mode reg read to use proper data offset. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Fix double buffering in dcn2 ICSCNoah Abradjian6-20/+135
[Why] When rapidly adjusting video brightness, screen tearing was observed. This was due to overwritten values in ICSC registers. In dcn10, this issue had been fixed by implementing double buffering via alternating ICSC modes. However, the second register set used in dcn1 doesn't exist in dcn2. [How] Create new program_input_csc for dcn20. Use ICSC_B registers instead of COMA registers as second set. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: expand dml structsDmytro Laktyushkin1-3/+32
Add more fields to support upcoming dml versions Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Don't always set pstate true if dummy latency = 0Alvin Lee1-1/+1
[Why] If dummy pstate latency is 0 we should report the actual pstate support, and not that pstate is always supported. [How] Don't always program pstate support true Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Add double buffering to dcn20 OCSCNoah Abradjian3-5/+57
[Why] When rapidly adjusting colour properties (e.g. brightness), screen tearing was observed. This was due to overwritten values in OCSC registers. In dcn10, this issue had been fixed by implementing double buffering by alternating OCSC modes. [How] Alternate which OCSC registers are used by switching modes each time. This double buffers the CSC writes. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Adding forgotten hubbub funcMartin Leung1-1/+2
[why] While doing seamless boot I made some changes to dcn2 hubbub functions, missed a link [how] link hubbub1 func to hubbub2 usage. It has already been successfully linked in dcn1 and 3. Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amd/display: Fix 300Hz Freesync bugAlvin Lee1-1/+3
Needed to reprogram vblank_start in dml properly in order to get the correct dlg params to program VTG. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-10drm/amd/display: MST DSC compute fair shareDavid Francis2-2/+6
If there is limited link bandwidth on a MST network, it must be divided fairly between the streams on that network Implement an algorithm to determine the correct DSC config for each stream The algorithm: This [ ] ( ) represents the range of bandwidths possible for a given stream. The [] area represents the range of DSC configs, and the () represents no DSC. The bandwidth used increases from left to right. First, try disabling DSC on all streams [ ] (|) [ ] (|) Check this against the bandwidth limits of the link and each branch (including each endpoint). If it passes, the job is done Second, try maximum DSC compression on all streams that support DSC [| ] ( ) [| ] ( ) If this does not pass, then enabling this combination of streams is impossible Otherwise, divide the remaining bandwidth evenly amongst the streams [ | ] ( ) [ | ] ( ) If one or more of the streams reach minimum compression, evenly divide the reamining bandwidth amongst the remaining streams [ |] ( ) [ |] ( ) [ | ] ( ) [ | ] ( ) If all streams can reach minimum compression, disable compression greedily [ |] ( ) [ |] ( ) [ ] (|) Perform this algorithm on each full update, on each MST link with at least one DSC stream on it After the configs are computed, call dcn20_add_dsc_to_stream_resource on each stream with DSC enabled. It is only after all streams are created that we can know which of them will need DSC. Do all of this at the end of amdgpu atomic check. If it fails, fail check; This combination of timings cannot be supported. v2: Use drm_dp_mst_atomic_check to validate bw for certain dsc configurations v3: Use dc_dsc_policy structure to get min and max bpp rate for DSC configuration Acked-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-10drm/amd/display: Initialize DSC PPS variables to 0David Francis1-0/+3
For DSC MST, sometimes monitors would break out in full-screen static. The issue traced back to the PPS generation code, where these variables were being used uninitialized and were picking up garbage. memset to 0 to avoid this Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/display: use true, false for bool variable in dcn20_hwseq.czhengbin1-2/+2
Fixes coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c:186:6-14: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c:189:2-10: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/display: fix kernel_fpu_begin/_end() warningsXiaojie Yuan1-2/+0
kernel_fpu_begin/_end() are already called inside dcn20_resource_construct, and calling kernel_fpu_begin/_end() recursively triggers WARN_ON() when CONFIG_X86_DEBUG_FPU is enabled. [ 107.060434] WARNING: CPU: 6 PID: 1370 at arch/x86/kernel/fpu/core.c:90 kernel_fpu_begin+0xbd/0xe0 <snip> [ 107.268197] Call Trace: [ 107.270751] dcn20_patch_bounding_box+0x17/0x100 [amdgpu] [ 107.276204] init_soc_bounding_box+0x1b3/0x5f0 [amdgpu] [ 107.281536] ? _cond_resched+0x19/0x30 [ 107.285307] dcn20_resource_construct+0x3a9/0xa90 [amdgpu] [ 107.290957] ? dcn20_resource_construct+0x3a9/0xa90 [amdgpu] [ 107.296621] ? __alloc_pages_nodemask+0x16a/0x330 [ 107.301476] ? _cond_resched+0x19/0x30 [ 107.305284] ? kmem_cache_alloc_trace+0x197/0x230 [ 107.310063] ? _cond_resched+0x19/0x30 [ 107.313783] ? kmem_cache_alloc_trace+0x197/0x230 [ 107.318691] dcn20_create_resource_pool+0x42/0x70 [amdgpu] [ 107.324315] dc_create_resource_pool+0x12d/0x170 [amdgpu] [ 107.329851] dc_create+0x1b8/0x6a0 [amdgpu] [ 107.334013] ? kmem_cache_alloc_trace+0x1e2/0x230 [ 107.338832] amdgpu_dm_init+0x13e/0x1c0 [amdgpu] <snip> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-13 21:21:42 +0300