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path: root/drivers/gpu/drm/amd/display/dc/dce110
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2018-02-19drm/amd/display: Fix null-derefs on non-dcn buildsRoman Li1-1/+2
Fixing regression introduced by 'Use real BE and FE index to program regs.' Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Fix check for setting input TFAndrew Jiang1-4/+6
We no longer change the plane state pointer for full updates, and as such, we weren't setting the input transfer function and programming the degamma registers when we are supposed to. Check for a full update, an input TF change, or a gamma change in the update flags instead to correct this. Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Use real BE and FE index to program regs.Yongqiang Sun2-9/+9
In case of some pipes are fused, pipe_idx should not be used to program pipe regs. Instead of that, BE and FE inst number should be used for reg index. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Disable eDP with a proper sequence.Yongqiang Sun2-3/+36
Proper sequence should be: disable backlight dp blank disable output edp power off In enable accelatate mode, all the encoder and controller are disabled, so move disable eDP to the function is the easiest way to implement. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Pass full 3x4 remap matrix for color transformKrunoslav Kovac1-81/+13
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Fix FBC topology changeRoman Li1-4/+19
With FBC enabled there was a potential null-deref on topology change due to hardcorded pipe index. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Eliminate several Maximus-specific code pathsKen Chalmers1-35/+0
This allows Maximus emulation to more closely mirror actual silicon execution. * Enable pool->base.display_clock creation on Maximus. * Enable rest of dce110_apply_ctx_to_hw on Maximus. * Remove apply_ctx_to_hw_fpga (no longer necessary with the full dce110_apply_ctx_to_hw enabled). * Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock for Maximus (this was the only fix-up necessary after enabling dce110_apply_ctx_to_hw; everything else works unmodified on Maximus). Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-20drm/amd/display: Call validate_fbc should_enable_fbcHarry Wentland1-23/+16
validate_fbc never fails a modeset. It's simply used to decide whether to use FBC or not. Calling it validate_fbc might be confusing to some so rename it to should_enable_fbc. With that let's also remove the DC_STATUS return code and return bool and make enable_fbc a void function since we never check it's return value and probably never want to anyways. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-20drm/amd/display: Remove dead enable_plane function definition and callHarry Wentland1-3/+0
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-14drm/amd/display: Remove redundant NULL check in DCE11 HWSSHarry Wentland1-2/+1
We already check this a couple lines earlier. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-14drm/amd/display: Move wait for hpd ready out from edp power control.Yongqiang Sun2-12/+8
It may take over 200ms for wait hpd ready. To optimize the resume time, we can power on eDP in init_hw, wait for hpd ready when doing link training. also create separate eDP enable function to make sure eDP is powered up before doing and DPCD access, as HPD low will result in DPDC transaction failure. After optimization, setpowerstate 145ms -> 9.8ms, DPMS 387ms -> 18.9ms Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-14drm/amd/display: Fix access of wrong array element TF format conversionHarry Wentland1-2/+2
Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:357 convert_to_custom_float() error: buffer overflow 'arr_points' 2 <= 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:358 convert_to_custom_float() warn: buffer overflow 'arr_points' 2 <= 2 Regression: drm/amd/display: Remove extra arr_points element Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-14drm/amd/display: Remove redundant checks in set_default_colorsHarry Wentland1-10/+2
pipe_ctx->stream and pipe_ctx->plane_state are never NULL Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2111 set_default_colors() error: we previously assumed 'pipe_ctx->stream' could be null (see line 2101) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-14drm/amd/display: Remove plane_res.mi check in dce110_apply_ctx_for_surfaceHarry Wentland1-7/+6
plane_res.mi (memory interface) can never be NULL for DCE110 Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2881 dce110_apply_ctx_for_surface() error: we previously assumed 'pipe_ctx->plane_res.mi' could be null (see line 2873) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-07drm/amdgpu: add license to files where it was missingAlex Deucher2-1/+24
These files were missing it before. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-07drm/amdgpu: add license to MakefilesAlex Deucher1-0/+21
Was missing license text. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Move update_plane_addr to apply_ctx_for_surface for dce.Yongqiang Sun1-0/+3
Move update_plane_addr to apply_ctx_for_surface, address update will just be called once, not twice for updat type is full and medium. This will reduce some reg access and duration time. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display/dc/dce110/dce110_mem_input_v: use swap macro in ↵Gustavo A. R. Silva1-20/+8
program_size_and_rotation Make use of the swap macro instead of _manually_ swapping values and remove unnecessary variable swap. This makes the code easier to read and maintain. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Fix unbalanced locking in surface applyRoman Li1-5/+2
also simplifying syntax and removing unused variable in dce110_apply_ctx_for_surface() Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Apply work around for stutter.Yongqiang Sun1-5/+5
Power on one plane after disable all the planes, for a hw bug work around to resolve stutter efficiency issue. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: A few more color indentation changesHarry Wentland1-52/+27
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Bunch more color indentation cleanupsHarry Wentland1-34/+20
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Remove extra arr_points elementHarry Wentland2-8/+1
arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: send display_count msg so SMU can enter S0i2Hersen Wu1-0/+5
SMU can future lower voltages in long idle case when all display is off. If all display output is turned off via DPMS, send display_count = 0 after all output are turned off. otherwise send display_count msg before turning on display to make sure SMU exit S0i2 state. before is not neccessary as we are out of S0i2 when driver execute code, but send message before anyways for correctness. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Fix some more color indentationsHarry Wentland1-22/+13
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Bunch of indentation cleanups in color stuffHarry Wentland1-6/+4
Trying to align with kernel coding style and make it a bit more readable. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Refactor disable front end pipes.Yongqiang Sun1-3/+7
There are different code to disable front end, it is difficult to debug and adding new process. This refactor makes all disable front end call the same functions. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Don't use dc_link in link_encoderAndrew Jiang2-22/+28
dc_link is at a higher level than link_encoder, and we only want higher-level components to be able to access lower-level ones, not the other way around. Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/display: Multi display synchronization logicMikita Lipski3-54/+263
This feature synchronizes multiple displays with various timings to a display with the highest refresh rate it is enabled if edid caps flag multi_display_sync is set to one There are limitations on refresh rates allowed that can be synchronized. That would prevent from underflow and other potential corruptions. Multi display synchronization is using the same functions as timing_sync in order to minimize redunduncy and decision to disable synchronization is based on trigger parametre set in DM Feature is developed for DCN1 and DCE11 Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-05drm/amd/display: Move hdr_metadata from plane to streamAnthony Koo1-2/+1
Need to move HDR Metadata from Surface to Stream since there is only one infoframe possible per stream. Also cleaning up some duplicate definitions. Signed-off-by: Anthony Koo <anthony.koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-05drm/amd/display: Move lock to front end program.Yongqiang Sun1-0/+16
Moved lock and unlock to apply_ctx_to_surface, since all the front end programming is within apply_ctx_to_surface. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-05drm/amd/display: Add APU cap in dc_capsAnthony Koo1-0/+1
Some features should only be enabled on APUs or should not be enabled on APUs. Signed-off-by: Anthony Koo <anthony.koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-11-29drm/amd/display: Fix use before NULL check in validate_timingHarry Wentland1-4/+4
Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1124 dce110_timing_generator_validate_timing() warn: variable dereferenced before check 'timing' (see line 1116) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-11-29drm/amd/display: fix seq issue: turn on clock before programming afmt.Charlene Liu1-12/+10
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-11-29drm/amd/display: fix memory leaks on error exit returnColin Ian King1-5/+7
Currently in the case where some of the allocations fail for dce110_tgv, dce110_xfmv, dce110_miv or dce110_oppv then the exit return path ends up leaking allocated objects. Fix this by kfree'ing them before returning. Also re-work the comparison of the null pointers to use the !ptr idiom. Detected by CoverityScan, CID#1460246, 1460325, 1460324, 1460392 ("Resource Leak") Fixes: c4562236b3bc ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-11-29drm/amd/display: check plane state before validating fbcShirish S1-0/+4
While validation fbc, array_mode of the pipe is accessed without checking plane_state exists for it. Causing to null pointer dereferencing followed by reboot when a crtc associated with external display(not connected) is page flipped. This patch adds a check for plane_state before using it to validate fbc. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-11-29drm/amd/display: Should disable when new stream is nullLeo (Sunpeng) Li1-2/+4
core_link_disable_stream should be called when the new stream is null (i.e. want to disable). Modify the if condition to reflect that. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-11-08amdgpu/dc: fix indentation warning from smatch.Dave Airlie1-15/+15
This fixes all the current smatch: warn: inconsistent indenting Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-27drm/amd/display: Fix no display on FijiJerry Zuo1-10/+9
Allocate memory for the second pipe allocate_mem_input() needs to be done prior to program pipe front end. It shows sensitive to Fiji. Failure to do so will cause error in allocate memory  allocate_mem_input() on the second connected display. Signed-off-by: Jerry Zuo <Jerry.Zuo@amd.com> Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display:: Fix NULL pointer in Raven hotplugJerry (Fangzhi) Zuo1-7/+0
Programming sequence to frontend and backend has been switched. In such case, program_scaler() is getting called when programming frontend, and should be removed from backend programming routine. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: LGD panel willl flash line under windowHersen Wu1-0/+9
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: fix null dereference in reset hw ctxEric Yang1-1/+1
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: rename struct mem_input to hubp for dcnYue Hin Lau1-9/+10
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Fixed switching mode half screen gamma incorrect.Yongqiang Sun1-0/+10
Half screen gamma setting and cursor are incorrect when switching mode through win+p due to wrong programming gamma sequence (In case of bottom pipe, gamma and cursor are programmed before front end programmed, pipe is power gated). change: 1. Cache curor attributes to stream 2. Move set gamma and cursor inside front end programming. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: add dpms state to DCHersen Wu1-7/+6
- avoid eDP screen flash 4 times when resume from s3 - improve s3 and boot time Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: audio dynamic resource acquired relatedCharlene Liu2-3/+11
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: make FBC configurable optionShirish S3-11/+11
Currently FBC is guarded with ENABLE_FBC macro, which needs to be manually enabled in Makefile. This patch moves it to Kconfig so that there wont be any need to additional patch to be carried for enabling or disabling on every SoC. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Move power control from link encoder to hwsequencerAndrew Jiang2-10/+151
A recent commit moved the backlight control code along with the register defines, but did not move the power control code. This along with remnant fields in the dce110_link_enc_registers struct made it so that the code still compiled, but any attempts to access the LVTMA_PWRSEQ_STATE register led to reading from an address of 0. This patch corrects that. Also, rename blacklight_control to edp_backlight_control (Typo fix). Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: make sure BL off to mainlink off has enough timeCharlene Liu1-7/+0
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: edp backlight regression fixYue Hin Lau1-0/+5
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-23 11:03:15 +0300