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path: root/drivers/gpu/drm/amd/amdgpu
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2021-03-24drm/amdgpu: add kdb loading support for psp v13Hawking Zhang1-0/+70
Add callback function to support key database firmware loading for psp v13 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu: init sos microcode for psp v13Hawking Zhang3-1/+89
Initialize sos microcode for aldebaran Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu: Print the IH client ID name when vm fault happensYong Zhao3-4/+40
This gives more information and improves productivity. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-16Merge tag 'drm-misc-next-2021-03-03' of ↵Dave Airlie14-49/+51
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.13: UAPI Changes: Cross-subsystem Changes: Core Changes: - %p4cc printk format modifier - atomic: introduce drm_crtc_commit_wait, rework atomic plane state helpers to take the drm_commit_state structure - dma-buf: heaps rework to return a struct dma_buf - simple-kms: Add plate state helpers - ttm: debugfs support, removal of sysfs Driver Changes: - Convert drivers to shadow plane helpers - arc: Move to drm/tiny - ast: cursor plane reworks - gma500: Remove TTM and medfield support - mxsfb: imx8mm support - panfrost: MMU IRQ handling rework - qxl: rework to better handle resources deallocation, locking - sun4i: Add alpha properties for UI and VI layers - vc4: RPi4 CEC support - vmwgfx: doc cleanup Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20210303100600.dgnkadonzuvfnu22@gilmour
2021-03-12Merge tag 'amd-drm-fixes-5.12-2021-03-10' of ↵Dave Airlie4-2/+7
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-5.12-2021-03-10: amdgpu: - Fix aux backlight control - Add a backlight override parameter - Various display fixes - PCIe DPM fix for vega - Polaris watermark fixes - Additional S0ix fix radeon: - Fix GEM regression - Fix AGP dependency handling Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210310221141.3974-1-alexander.deucher@amd.com
2021-03-11drm/amdgpu: fix S0ix handling when the CONFIG_AMD_PMC=mAlex Deucher1-1/+1
Need to check the module variant as well. Acked-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-03-11drm/amdgpu: fb BO should be ttm_bo_type_deviceNirmoy Das1-1/+1
FB BO should not be ttm_bo_type_kernel type and amdgpufb_create_pinned_object() pins the FB BO anyway. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-11drm/amd/display: Add a backlight module optionTakashi Iwai2-0/+5
There seem devices that don't work with the aux channel backlight control. For allowing such users to test with the other backlight control method, provide a new module option, aux_backlight, to specify enabling or disabling the aux backport support explicitly. As default, the aux support is detected by the hardware capability. v2: make the backlight option generic in case we add future backlight types (Alex) BugLink: https://bugzilla.opensuse.org/show_bug.cgi?id=1180749 BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1438 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-03-10drm/amdgpu: add aldebaran sdma firmware support (v2)Kevin Wang1-3/+9
add sdma firmware load support for soc model v2: drop some emulator leftovers (Alex) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdkfd: Add Aldebaran KFD supportYong Zhao2-0/+2
Add initial KFD support. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: set ip blocks for aldebaranLe Ma1-0/+1
Set ip blocks and asic family id Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: correct mmBIF_SDMA4_DOORBELL_RANGE address for aldebaranLe Ma1-4/+14
On aldebaran, mmBIF_SDMA4_DOORBELL_RANGE isn't right next to mmBIF_SDMA3_DOORBELL_RANGE. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add sdma block support for aldebaranLe Ma1-0/+5
Add initial sdma support for aldebaran, and this asic has 5 sdma instances. v2: remove adundant condition check Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <Evan.Quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add gfx v9 block support for aldebaranLe Ma1-1/+21
Add gfx initial support Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: set fw load type for aldebaranLe Ma1-0/+2
Set backdoor loading way in current phase v2: change case location to not break other asics Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add gmc v9 block support for AldebaranLe Ma1-0/+3
Add gfx memory controller support Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add mmhub support for aldebaran (v3)Le Ma3-1/+642
v1: dupilcate mmhub_v1_7.c from mmhub_v1_0.c because mmhub register address for aldebaran is different from existing asics (Le) v2: switch to latest mmhub_v9_4_2 register headers (Hawking) v3: squash in init VM_L2_CNTL3 default value for mmhub v1_7 Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add soc15 common ip block support for aldebaranLe Ma1-2/+17
Initialize aldebaran common ip block Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add gpu_info fw parse support for aldebaranLe Ma1-0/+4
Parses asic configurations stored in gpu_info firmware and make them available for driver to use. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add register base init for aldebaran (v2)Le Ma4-1/+59
v1: add aldebaran_reg_base_init function to initialize register base for aldebaran (Le) v2: update VCN HWIP and initialize base offset (James) Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add aldebaran asic typeLe Ma1-0/+1
Add aldebaran in amdgpu_asic_name array and amdgpu_asic_type enum Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amd/display: Add a backlight module optionTakashi Iwai2-0/+5
There seem devices that don't work with the aux channel backlight control. For allowing such users to test with the other backlight control method, provide a new module option, aux_backlight, to specify enabling or disabling the aux backport support explicitly. As default, the aux support is detected by the hardware capability. v2: make the backlight option generic in case we add future backlight types (Alex) BugLink: https://bugzilla.opensuse.org/show_bug.cgi?id=1180749 BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1438 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: enable TMZ by default on Raven asicsAlex Deucher2-2/+12
This has been stable for a while. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: Fix some unload driver issuesEmily Deng1-0/+1
If have memory leak, maybe it will have issue in ttm_bo_force_list_clean-> ttm_mem_evict_first. Set adev->gart.ptr to null to avoid to call amdgpu_gmc_set_pte_pde to cause ptr issue pointer when calling amdgpu_gart_unbind in amdgpu_bo_fini which is after gart_fini. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: Fix some unload driver issuesEmily Deng2-2/+4
When unloading driver after killing some applications, it will hit sdma flush tlb job timeout which is called by ttm_bo_delay_delete. So to avoid the job submit after fence driver fini, call ttm_bo_lock_delayed_workqueue before fence driver fini. And also put drm_sched_fini before waiting fence. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amd/amdgpu: add fini virt data exchange to ip_suspendJingwen Chen1-1/+3
[Why] when try to shutdown guest vm in sriov mode, virt data exchange is not fini. After vram lost, trying to write vram could hang cpu. [How] add fini virt data exchange in ip_suspend Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Jack Zhang <Jack.Zhang1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: add sdma 4_x interrupts printingFeifei Xu2-0/+120
Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE interrupt info printing. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.Feifei Xu1-15/+4
SDMA 4_x asics share the same MGCG/MGLS setting. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: add DMUB trace event IRQ source defineLeo (Hanghong) Ma1-0/+1
[Why & How] We use DMCUB outbox0 interrupt to log DMCUB trace buffer events as Linux kernel traces, so need to add some irq source related defination in the header files; Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: enable one vf mode on sienna cichlid vfHorace Chen1-0/+2
sienna cichlid needs one vf mode which allows vf to set and get clock status from guest vm. So now expose the required interface and allow some smu request on VF mode. Also since this asic blocked direct MMIO access, use KIQ to send SMU request under sriov vf. OD use same command as getting pp table which is not allowed for sienna cichlid, so remove OD feature under sriov vf. Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Monk Liu<monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05Merge tag 'amd-drm-fixes-5.12-2021-03-03' of ↵Dave Airlie4-7/+8
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-5.12-2021-03-03: amdgpu: - S0ix fix - Handle new NV12 SKU - Misc power fixes - Display uninitialized value fix - PCIE debugfs register access fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210304043255.3792-1-alexander.deucher@amd.com
2021-03-04drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcieKevin Wang1-2/+2
the register offset isn't needed division by 4 to pass RREG32_PCIE() Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-03-04drm/amdgpu: enable BACO runpm by default on sienna cichlid and navy flounderAlex Deucher1-2/+0
It works fine and was only disabled because primary GPUs don't enter runpm if there is a console bound to the fbdev due to the kmap. This will at least allow runpm on secondary cards. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-04drm/amdgpu:disable VCN for Navi12 SKUAsher.Song1-2/+4
Navi12 0x7360/C7 SKU has no video support, so remove it. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Asher.Song <Asher.Song@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-03-04drm/amdgpu: Only check for S0ix if AMD_PMC is configuredAlex Deucher1-1/+2
The S0ix check only makes sense if the AMD PMC driver is present. We need to use the legacy S3 pathes when the PMC driver is not present. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-03-03drm/amdgpu: correct DRM_ERROR for kvmalloc_arrayChen Li1-1/+1
This may avoid debug confusion. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chen Li <chenli@uniontech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: Use kvmalloc for CS chunksChen Li1-6/+6
The number of chunks/chunks_array may be passed in by userspace and can be large. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chen Li <chenli@uniontech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: Remove unnecessary conversion to boolJiapeng Chong1-1/+1
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2252:40-45: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcieKevin Wang1-2/+2
the register offset isn't needed division by 4 to pass RREG32_PCIE() Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: add SECURE DISPLAY TA firmware info in debugfsKevin Wang1-0/+5
add SECUREDISPLAY TA firmware info in amdgpu_fimrware_info() Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: refine PSP TA firmware info print in debugfsKevin Wang2-30/+20
refine PSP TA firmware info print in amdgpu_firmware_info(). Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amdgpu: enable BACO runpm by default on sienna cichlid and navy flounderAlex Deucher1-2/+0
It works fine and was only disabled because primary GPUs don't enter runpm if there is a console bound to the fbdev due to the kmap. This will at least allow runpm on secondary cards. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amdgpu: Only check for S0ix if AMD_PMC is configuredAlex Deucher1-1/+2
The S0ix check only makes sense if the AMD PMC driver is present. We need to use the legacy S3 pathes when the PMC driver is not present. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amdgpu: add missing df counter disable writeJonathan Kim1-0/+2
Request to stop DF performance counters is missing the actual write to the controller register. Reported-by: Chris Freehill <chris.freehill@amd.com> Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amdgpu: correct TA RAP firmware information print errorKevin Wang1-1/+1
miss RAP TA in loop. (when i == 4) Fix: drm/amdgpu: add RAP TA version print in amdgpu_firmware_info Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reported-by: Candice Li <candice.li@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-27drm/amdgpu: remove unnecessary reading for epprom headerDennis Li5-54/+8
If the number of badpage records exceed the threshold, driver has updated both epprom header and control->tbl_hdr.header before gpu reset, therefore GPU recovery thread no need to read epprom header directly. v2: merge amdgpu_ras_check_err_threshold into amdgpu_ras_eeprom_check_err_threshold Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-27drm/amdgpu: add RAP TA version print in amdgpu_firmware_infoKevin Wang1-0/+8
add RAP TA version print in amdgpu_firmware_info. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-27drm/amdgpu: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTEYang Li1-2/+2
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1589:0-23: WARNING: fops_ib_preempt should be defined with DEFINE_DEBUGFS_ATTRIBUTE ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1592:0-23: WARNING: fops_sclk_set should be defined with DEFINE_DEBUGFS_ATTRIBUTE Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-27drm/amdgpu/codec: drop the internal codec indexAlex Deucher7-79/+80
And just use the ioctl index. They are the same. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-27drm/amdgpu: bump driver version for new video codec INFO ioctl queryAlex Deucher1-1/+2
So mesa can check when to query the kernel vs use hardcoded codec bandwidth data. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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