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path: root/drivers/gpu/drm/amd/amdgpu/nv.c
AgeCommit message (Expand)AuthorFilesLines
2020-10-05drm/amdgpu: enable gfx clock gating and power gating for vangoghHuang Rui1-2/+5
2020-10-05drm/amdgpu: IP discovery table is not ready yet for VGAlex Deucher1-0/+4
2020-10-05drm/amdgpu: enable psp support for vangoghHuang Rui1-0/+2
2020-10-05drm/amdgpu: add smu ip block for vangoghHuang Rui1-0/+1
2020-10-05drm/amdgpu: add nbio v7.2 for vangogh (v2)Huang Rui1-2/+8
2020-10-05drm/amdgpu: add pcie port indirect read and write on nvHuang Rui1-0/+32
2020-10-05drm/amdgpu: enable vcn3.0 for van goghThong Thai1-0/+2
2020-10-05drm/amdgpu: set ip blocks for van goghHuang Rui1-0/+9
2020-10-05drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)Huang Rui1-1/+2
2020-10-05drm/amdgpu: add nv common ip block support for van goghHuang Rui1-0/+8
2020-10-01drm/amdgpu: switch to indirect reg access helperHawking Zhang1-43/+8
2020-09-23drm/amdgpu: fix hdp register access errorStanley.Yang1-1/+1
2020-09-16drm/amdgpu: Fix consecutive DPC recovery failures.Andrey Grodzovsky1-2/+2
2020-08-26drm/amdgpu: use MODE1 reset for navy_flounder by defaultJiansong Chen1-0/+1
2020-08-26drm/amdgpu: add pre_asic_init callback for naviAlex Deucher1-0/+5
2020-08-15drm/amdgpu: note what type of reset we are usingAlex Deucher1-2/+4
2020-08-08drm/amdgpu: use mode1 reset by default for sienna_cichlidLikun Gao1-3/+8
2020-07-23drm/amdgpu: expand sienna chichlid reg access supportJohn Clements1-0/+45
2020-07-21drm/amdgpu: enable xgmi support for sienna cichlidJohn Clements1-0/+3
2020-07-15drm/amdgpu: enable ih CG for navy_flounderJiansong Chen1-1/+2
2020-07-15drm/amdgpu: enable hdp CG and LS for navy_flounderJiansong Chen1-1/+3
2020-07-15drm/amdgpu: enable mc CG and LS for navy_flounderJiansong Chen1-1/+3
2020-07-15drm/amdgpu: enable athub/mmhub PG for navy_flounderJiansong Chen1-1/+3
2020-07-15drm/amd/display: add DC support for navy flounderBhawanpreet Lakha1-0/+4
2020-07-15drm/amdgpu: enable GFX clock gating for navy_flounderJiansong Chen1-1/+4
2020-07-15drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+4
2020-07-15drm/amdgpu: enable VCN3.0 DPG for navy_flounderBoyuan Zhang1-1/+2
2020-07-15drm/amdgpu: enable VCN3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+2
2020-07-15drm/amdgpu: add vcn ip block for navy_flounderBoyuan Zhang1-0/+2
2020-07-15drm/amdgpu: add psp block for navy_flounderJiansong Chen1-0/+5
2020-07-15drm/amdgpu: add smu block for navy_flounderJiansong Chen1-0/+3
2020-07-15drm/amdgpu: add virtual display support for navy_flounder.Jiansong Chen1-0/+2
2020-07-15drm/amdgpu: add sdma ip block for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu: add ih ip block for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu: add gmc ip block for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu: add common ip block for navy_flounderJiansong Chen1-0/+3
2020-07-15drm/amdgpu: initialize IP offset for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu/soc15: add support for navy_flounderJiansong Chen1-0/+7
2020-07-15drm/amd/sriov skip jped ip block and close pgcg flagsJack Zhang1-1/+8
2020-07-15drm/amdgpu: add module parameter choose reset modeWenhui Sheng1-0/+8
2020-07-15drm/amdgpu: enable mode1 resetWenhui Sheng1-7/+12
2020-07-08drm/amdgpu: fix coding error of mmhub pg enablementLikun Gao1-3/+3
2020-07-02drm/amdgpu: request init data in virt detectionWenhui Sheng1-6/+5
2020-07-01drm/amdgpu: Enable DM block for DCN3Bhawanpreet Lakha1-0/+4
2020-07-01drm/amdgpu: enable DPG mode for VCN3.0Boyuan Zhang1-0/+1
2020-07-01drm/amd/powerplay: enable mmhub pgKenneth Feng1-1/+2
2020-07-01drm/amd/powerplay: enable athub pgKenneth Feng1-1/+2
2020-07-01drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOVshaoyunl1-1/+1
2020-07-01drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid.Likun Gao1-0/+1
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