starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-11-11	zynq-fpga: Only route PR via PCAP when required	Mike Looijmans	1	-0/+4
2018-10-16	fpga: mgr: add devm_fpga_mgr_create	Alan Tull	1	-3/+2
2018-05-25	fpga: manager: change api, don't use drvdata	Alan Tull	1	-3/+11
2017-03-17	fpga: zynq: Add support for encrypted bitstreams	Moritz Fischer	1	-3/+25
2017-02-10	fpga zynq: Use the scatterlist interface	Jason Gunthorpe	1	-39/+135
2017-02-10	fpga zynq: Check the bitstream for validity	Jason Gunthorpe	1	-0/+21
2017-02-10	fpga zynq: Check for errors after completing DMA	Jason Gunthorpe	1	-22/+32
2016-11-30	fpga zynq: Fix incorrect ISR state on bootup	Jason Gunthorpe	1	-7/+10
2016-11-30	fpga zynq: Remove priv->dev	Jason Gunthorpe	1	-11/+8
2016-11-30	fpga zynq: Add missing \n to messages	Jason Gunthorpe	1	-11/+11
2016-11-10	fpga-mgr: add fpga image information struct	Alan Tull	1	-4/+6
2015-10-24	fpga: zynq-fpga: Fix issue with drvdata being overwritten.	Moritz Fischer	1	-3/+4
2015-10-24	fpga: zynq-fpga: Change fw format to handle bin instead of bit.	Moritz Fischer	1	-22/+2
2015-10-24	fpga: zynq-fpga: Fix unbalanced clock handling	Moritz Fischer	1	-2/+2
2015-10-18	fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000	Moritz Fischer	1	-0/+533