summaryrefslogtreecommitdiff
path: root/drivers/cxl/pci.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-09cxl: fix cxl_report_and_clear() RAS UE addr mis-assignmentDave Jiang1-2/+5
2022-12-07cxl/pci: Remove endian confusionDan Williams1-4/+3
2022-12-07cxl/pci: Add some type-safety to the AER trace pointsDan Williams1-2/+2
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-40/+173
2022-12-05cxl/port: Add RCD endpoint port enumerationDan Williams1-0/+10
2022-12-04cxl/pci: Add callback to log AER correctable errorDave Jiang1-0/+20
2022-12-04cxl/pci: Add (hopeful) error handling supportDan Williams1-0/+137
2022-12-04cxl/pci: add tracepoint events for CXL RASDave Jiang1-0/+2
2022-12-04cxl/pci: Find and map the RAS Capability StructureDan Williams1-0/+8
2022-12-04cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-19/+6
2022-12-04cxl/pci: Kill cxl_map_regs()Dan Williams1-22/+1
2022-12-03cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams1-3/+0
2022-11-14cxl/doe: Request exclusive DOE accessIra Weiny1-0/+5
2022-07-20cxl/pci: Create PCI DOE mailbox's for memory devicesIra Weiny1-0/+44
2022-07-10cxl/mem: Convert partition-info to resourcesDan Williams1-1/+1
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams1-135/+0
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams1-44/+1
2022-05-19cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()Dan Williams1-4/+0
2022-05-19cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams1-2/+2
2022-04-13cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pciDan Williams1-9/+18
2022-04-13cxl/pci: Add debug for DVSEC range init failuresDan Williams1-3/+10
2022-04-13cxl/mbox: Use new return_code handlingDavidlohr Bueso1-1/+2
2022-04-13cxl/mbox: Improve handling of mbox_cmd hw return codesDavidlohr Bueso1-1/+1
2022-04-13cxl/pci: Use CXL_MBOX_SUCCESS to check against mbox_cmd return codeDavidlohr Bueso1-2/+2
2022-04-08cxl/pci: Drop shadowed variableDan Williams1-1/+0
2022-02-09cxl/pci: Emit device serial numberDan Williams1-0/+1
2022-02-09cxl/pci: Implement wait for media activeBen Widawsky1-1/+48
2022-02-09cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky1-0/+119
2022-02-09cxl/pci: Cache device DVSEC offsetBen Widawsky1-0/+6
2022-02-09cxl/pci: Store component register base in cxldsBen Widawsky1-0/+11
2022-02-09cxl/pci: Rename pci.h to cxlpci.hDan Williams1-1/+1
2022-02-09cxl/acpi: Map component registers for Root PortsBen Widawsky1-52/+0
2022-02-09cxl: Flesh out register namesBen Widawsky1-7/+7
2022-02-09cxl/pci: Defer mailbox status checks to command timeoutsDan Williams1-101/+33
2022-02-09cxl/pci: Implement Interface Ready TimeoutBen Widawsky1-0/+35
2021-11-15cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny1-60/+60
2021-10-29cxl/pci: Use pci core's DVSEC functionalityBen Widawsky1-24/+2
2021-10-29cxl/pci: Split cxl_pci_setup_regs()Ben Widawsky1-36/+37
2021-10-29cxl/pci: Add @base to cxl_register_mapDan Williams1-15/+16
2021-10-29cxl/pci: Make more use of cxl_register_mapBen Widawsky1-34/+25
2021-10-29cxl/pci: Remove pci request/release regionsBen Widawsky1-5/+0
2021-10-29cxl/pci: Fix NULL vs ERR_PTR confusionDan Williams1-1/+1
2021-10-29cxl/pci: Remove dev_dbg for unknown register blocksBen Widawsky1-3/+0
2021-09-22cxl/pci: Disambiguate cxl_pci further from cxl_memBen Widawsky1-33/+35
2021-09-21cxl/pci: Use module_pci_driverDan Williams1-22/+8
2021-09-21cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the coreDan Williams1-922/+2
2021-09-21cxl/pci: Drop idr.hDan Williams1-1/+0
2021-09-21cxl/mbox: Introduce the mbox_send operationDan Williams1-55/+21
2021-09-21cxl/pci: Clean up cxl_mem_get_partition_info()Dan Williams1-24/+11
2021-09-21cxl/pci: Make 'struct cxl_mem' device type genericDan Williams1-40/+35
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-28 19:43:27 +0300