starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-07-20	cxl/pci: Create PCI DOE mailbox's for memory devices	Ira Weiny	1	-0/+44
2022-07-10	cxl/mem: Convert partition-info to resources	Dan Williams	1	-1/+1
2022-05-19	cxl/mem: Consolidate CXL DVSEC Range enumeration in the core	Dan Williams	1	-135/+0
2022-05-19	cxl/pci: Move cxl_await_media_ready() to the core	Dan Williams	1	-44/+1
2022-05-19	cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()	Dan Williams	1	-4/+0
2022-05-19	cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()	Dan Williams	1	-2/+2
2022-04-13	cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pci	Dan Williams	1	-9/+18
2022-04-13	cxl/pci: Add debug for DVSEC range init failures	Dan Williams	1	-3/+10
2022-04-13	cxl/mbox: Use new return_code handling	Davidlohr Bueso	1	-1/+2
2022-04-13	cxl/mbox: Improve handling of mbox_cmd hw return codes	Davidlohr Bueso	1	-1/+1
2022-04-13	cxl/pci: Use CXL_MBOX_SUCCESS to check against mbox_cmd return code	Davidlohr Bueso	1	-2/+2
2022-04-08	cxl/pci: Drop shadowed variable	Dan Williams	1	-1/+0
2022-02-09	cxl/pci: Emit device serial number	Dan Williams	1	-0/+1
2022-02-09	cxl/pci: Implement wait for media active	Ben Widawsky	1	-1/+48
2022-02-09	cxl/pci: Retrieve CXL DVSEC memory info	Ben Widawsky	1	-0/+119
2022-02-09	cxl/pci: Cache device DVSEC offset	Ben Widawsky	1	-0/+6
2022-02-09	cxl/pci: Store component register base in cxlds	Ben Widawsky	1	-0/+11
2022-02-09	cxl/pci: Rename pci.h to cxlpci.h	Dan Williams	1	-1/+1
2022-02-09	cxl/acpi: Map component registers for Root Ports	Ben Widawsky	1	-52/+0
2022-02-09	cxl: Flesh out register names	Ben Widawsky	1	-7/+7
2022-02-09	cxl/pci: Defer mailbox status checks to command timeouts	Dan Williams	1	-101/+33
2022-02-09	cxl/pci: Implement Interface Ready Timeout	Ben Widawsky	1	-0/+35
2021-11-15	cxl/memdev: Change cxl_mem to a more descriptive name	Ira Weiny	1	-60/+60
2021-10-29	cxl/pci: Use pci core's DVSEC functionality	Ben Widawsky	1	-24/+2
2021-10-29	cxl/pci: Split cxl_pci_setup_regs()	Ben Widawsky	1	-36/+37
2021-10-29	cxl/pci: Add @base to cxl_register_map	Dan Williams	1	-15/+16
2021-10-29	cxl/pci: Make more use of cxl_register_map	Ben Widawsky	1	-34/+25
2021-10-29	cxl/pci: Remove pci request/release regions	Ben Widawsky	1	-5/+0
2021-10-29	cxl/pci: Fix NULL vs ERR_PTR confusion	Dan Williams	1	-1/+1
2021-10-29	cxl/pci: Remove dev_dbg for unknown register blocks	Ben Widawsky	1	-3/+0
2021-09-22	cxl/pci: Disambiguate cxl_pci further from cxl_mem	Ben Widawsky	1	-33/+35
2021-09-21	cxl/pci: Use module_pci_driver	Dan Williams	1	-22/+8
2021-09-21	cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the core	Dan Williams	1	-922/+2
2021-09-21	cxl/pci: Drop idr.h	Dan Williams	1	-1/+0
2021-09-21	cxl/mbox: Introduce the mbox_send operation	Dan Williams	1	-55/+21
2021-09-21	cxl/pci: Clean up cxl_mem_get_partition_info()	Dan Williams	1	-24/+11
2021-09-21	cxl/pci: Make 'struct cxl_mem' device type generic	Dan Williams	1	-40/+35
2021-09-07	cxl/pci: Fix debug message in cxl_probe_regs()	Li Qiang (Johnny Li)	1	-2/+2
2021-09-07	cxl/pci: Fix lockdown level	Dan Williams	1	-1/+1
2021-08-11	cxl/mem: Adjust ram/pmem range to represent DPA ranges	Ira Weiny	1	-8/+6
2021-08-10	cxl/mem: Account for partitionable space in ram/pmem ranges	Ira Weiny	1	-5/+91
2021-08-07	cxl/pci: Store memory capacity values	Ira Weiny	1	-3/+33
2021-08-06	cxl/pci: Simplify register setup	Ben Widawsky	1	-26/+12
2021-08-06	cxl/pci: Ignore unknown register block types	Ben Widawsky	1	-8/+12
2021-08-06	cxl/core: Move memdev management to core	Ben Widawsky	1	-227/+1
2021-08-06	cxl/pci: Introduce cdevm_file_operations	Dan Williams	1	-27/+38
2021-08-06	cxl: Move cxl_core to new directory	Ben Widawsky	1	-1/+1
2021-06-18	cxl/pci: Rename CXL REGLOC ID	Ben Widawsky	1	-1/+1
2021-06-16	cxl/pmem: Register 'pmem' / cxl_nvdimm devices	Dan Williams	1	-6/+17
2021-06-15	cxl/pci: Add media provisioning required commands	Ben Widawsky	1	-0/+19