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path: root/drivers/crypto
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2023-04-14starfive: copyright: modify related descriptionWilliam Qiu6-48/+30
Modify related description. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-02-24crypto: starfive - fix recursive mutex_lockTan En De3-1/+6
In jh7110_rsa_domain_transfer(), there is a path that may lead to recursive mutex_lock when calling jh7110_pka_wait_done(). Replace it with completion variable, which is more suitable for signaling completion instead of using mutex, not to mention using mutex_*() in interrupt context is bad. Signed-off-by: Tan En De <ende.tan@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
2023-02-16CR_3349: crypto: starfive - Remove AES key zeroizationJia Jie Ho1-2/+0
Remove key zeroization after each request in AES module. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
2022-11-01CR_2517:crypto:starfive: Fix "Unbalanced pm_runtime_enable!" warningJia Jie Ho1-1/+3
Crypto driver will probe multiple times waiting for DMA to be ready, each time calling pm_runtime_enable(). Only call pm_runtime_enable() when it's not already enabled. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
2022-10-27sec:starfive:add sec runtime PM opsWilliam Qiu3-0/+29
add sec runtime PM ops. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2022-10-14Merge branch 'CR_2285_SEC_jiajie.ho' into 'jh7110-5.15.y-devel'andy.hu4-605/+2
Cr 2285 sec jiajie.ho See merge request sdk/linux!533
2022-10-14CR_2285:SEC:Crypto:Starfive: Update hardware engine DMA driverjiajie.ho4-605/+2
Updating Starfive Jh7110 Crypto hardware engine to use orginal ARM PL08X driver. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-10-04CR_2141:crypto:starfive: Enhanced AES driver to handle negative casesjiajie.ho2-59/+83
1. Added input text length check for ECB and CBC mode. 2. Added input IV check for CCM mode. 3. Removed unnecessary zero data check. 4. Updated functions to return proper error codes. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-09-22CR_1737:crypto:starfive: Fixed AEAD tag generation and verificationjiajie.ho4-43/+81
Added support in AES GCM and CCM mode for various tag length and tag verification for non-AES blocksize aligned text. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-09-16Merge branch 'CR_1706_SEC_jiajie.ho' into 'jh7110-5.15.y-devel'andy.hu2-133/+184
CR_1706:crypto:starfive: Add buffer alignment for AES driver See merge request sdk/linux!394
2022-08-29CR_2015:crypto:starfive: Remove DES/TDES supportjiajie.ho6-852/+10
Removing DES and TDES support from Starfive crypto driver as these 2 algorithms have been deprecated by NIST. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-08-24CR_1831:crypto:starfive: Add fallback algo for crypto driversjiajie.ho3-305/+382
Add software fallback for RSA driver to support key sizes > 2Kb. Add software fallback for Hash driver for smaller input data blocksize to improve overall hash module efficiency. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-08-17CR_1706:crypto:starfive: Add buffer alignment for AES driverjiajie.ho2-133/+184
Added data alignment functions in AES driver to handle cases with unaligned/out-of-place data buffer. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-08-16CR_1662:crypto:starfive: Add delay for each CPU data write to enginejiajie.ho1-2/+6
Add a short delay to allow computations for previous block of data to complete before writing the next block of data to hw engine. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-08-10CR_1675:crypto:starfive: Add iv_out read after encryptionjiajie.ho1-0/+16
Add iv_out read required by Linux Self Test from hw engine after AES encryption has been completed. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-07-21crypto:starfive: Include bug fixes for hash/hmac found by Linux selftest.jiajie.ho1-9/+14
SHA/HMAC fixes: 1. Updated SM3 blocksize and digestsize. 2. Fixed non 32bit-aligned key input for HMAC. 3. Removed unnecessary init sequence check from SHA/HMAC. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-07-20crypto:starfive: Switch CSR polling instead of interrupt for HMAC.jiajie.ho3-8/+4
Observed interrupt signal goes HIGH before HMAC calculations has been completed. Switching to use CSR polling to check for HMAC_DONE instead. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
2022-07-04crypto:starfive:remove sha warning logwilliam.qiu1-21/+0
remove sha warning log Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-07-03crypto:starfive: Enable CCM and GCM mode for AESjiajie.ho3-126/+131
Add CCM and GCM modes of operation for Starfive AES driver. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-07-01PMU: Power Domain Controller Driver for JH7110 SOCWalker Chen1-3/+10
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-06-24crypto:starfive:Fix SHA-HMAC driverjiajie.ho4-64/+43
Fix HMAC setkey function and interrupt handling for SHA-HMAC Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-06-08reset:starfive:trng/crypto:shares a reset signalwilliam.qiu1-1/+1
Use devm_reset_control_get_shared to share a reset signal otherwise TRNG and crypto will not work at the same time. Signed-off-by: samin.guo <samin.guo@starfivetech.com>
2022-05-19crypto:starfive:fix clock diable errorwilliam.qiu1-3/+0
Cancel the state that the encrypted clock is disabled by default Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-05-06crypto:starfive:fix format problemwilliam.qiu2-82/+82
Fix the problem that some parameters in the header file are not aligned Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28crypto:starfive:jh7110: add crypto driver for starfive jh7110 soc.william.qiu14-0/+5998
add crypto driver for starfive jh7110 soc. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28crypto: add patch for 5.15william.qiu1-0/+33
crypto need this patch to work. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2021-09-24crypto: ccp - fix resource leaks in ccp_run_aes_gcm_cmd()Dan Carpenter1-6/+8
There are three bugs in this code: 1) If we ccp_init_data() fails for &src then we need to free aad. Use goto e_aad instead of goto e_ctx. 2) The label to free the &final_wa was named incorrectly as "e_tag" but it should have been "e_final_wa". One error path leaked &final_wa. 3) The &tag was leaked on one error path. In that case, I added a free before the goto because the resource was local to that block. Fixes: 36cf515b9bbe ("crypto: ccp - Enable support for AES GCM on v5 CCPs") Reported-by: "minihanshen(沈明航)" <minihanshen@tencent.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: John Allen <john.allen@amd.com> Tested-by: John Allen <john.allen@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-09-08Merge tag 'pci-v5.15-changes' of ↵Linus Torvalds1-3/+1
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Convert controller drivers to generic_handle_domain_irq() (Marc Zyngier) - Simplify VPD (Vital Product Data) access and search (Heiner Kallweit) - Update bnx2, bnx2x, bnxt, cxgb4, cxlflash, sfc, tg3 drivers to use simplified VPD interfaces (Heiner Kallweit) - Run Max Payload Size quirks before configuring MPS; work around ASMedia ASM1062 SATA MPS issue (Marek Behún) Resource management: - Refactor pci_ioremap_bar() and pci_ioremap_wc_bar() (Krzysztof Wilczyński) - Optimize pci_resource_len() to reduce kernel size (Zhen Lei) PCI device hotplug: - Fix a double unmap in ibmphp (Vishal Aslot) PCIe port driver: - Enable Bandwidth Notification only if port supports it (Stuart Hayes) Sysfs/proc/syscalls: - Add schedule point in proc_bus_pci_read() (Krzysztof Wilczyński) - Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure (Krzysztof Wilczyński) - Return "int" from pciconfig_read() syscall (Krzysztof Wilczyński) Virtualization: - Extend "pci=noats" to also turn on Translation Blocking to protect against some DMA attacks (Alex Williamson) - Add sysfs mechanism to control the type of reset used between device assignments to VMs (Amey Narkhede) - Add support for ACPI _RST reset method (Shanker Donthineni) - Add ACS quirks for Cavium multi-function devices (George Cherian) - Add ACS quirks for NXP LX2xx0 and LX2xx2 platforms (Wasim Khan) - Allow HiSilicon AMBA devices that appear as fake PCI devices to use PASID and SVA (Zhangfei Gao) Endpoint framework: - Add support for SR-IOV Endpoint devices (Kishon Vijay Abraham I) - Zero-initialize endpoint test tool parameters so we don't use random parameters (Shunyong Yang) APM X-Gene PCIe controller driver: - Remove redundant dev_err() call in xgene_msi_probe() (ErKun Yang) Broadcom iProc PCIe controller driver: - Don't fail devm_pci_alloc_host_bridge() on missing 'ranges' because it's optional on BCMA devices (Rob Herring) - Fix BCMA probe resource handling (Rob Herring) Cadence PCIe driver: - Work around J7200 Link training electrical issue by increasing delays in LTSSM (Nadeem Athani) Intel IXP4xx PCI controller driver: - Depend on ARCH_IXP4XX to avoid useless config questions (Geert Uytterhoeven) Intel Keembay PCIe controller driver: - Add Intel Keem Bay PCIe controller (Srikanth Thokala) Marvell Aardvark PCIe controller driver: - Work around config space completion handling issues (Evan Wang) - Increase timeout for config access completions (Pali Rohár) - Emulate CRS Software Visibility bit (Pali Rohár) - Configure resources from DT 'ranges' property to fix I/O space access (Pali Rohár) - Serialize INTx mask/unmask (Pali Rohár) MediaTek PCIe controller driver: - Add MT7629 support in DT (Chuanjia Liu) - Fix an MSI issue (Chuanjia Liu) - Get syscon regmap ("mediatek,generic-pciecfg"), IRQ number ("pci_irq"), PCI domain ("linux,pci-domain") from DT properties if present (Chuanjia Liu) Microsoft Hyper-V host bridge driver: - Add ARM64 support (Boqun Feng) - Support "Create Interrupt v3" message (Sunil Muthuswamy) NVIDIA Tegra PCIe controller driver: - Use seq_puts(), move err_msg from stack to static, fix OF node leak (Christophe JAILLET) NVIDIA Tegra194 PCIe driver: - Disable suspend when in Endpoint mode (Om Prakash Singh) - Fix MSI-X address programming error (Om Prakash Singh) - Disable interrupts during suspend to avoid spurious AER link down (Om Prakash Singh) Renesas R-Car PCIe controller driver: - Work around hardware issue that prevents Link L1->L0 transition (Marek Vasut) - Fix runtime PM refcount leak (Dinghao Liu) Rockchip DesignWare PCIe controller driver: - Add Rockchip RK356X host controller driver (Simon Xue) TI J721E PCIe driver: - Add support for J7200 and AM64 (Kishon Vijay Abraham I) Toshiba Visconti PCIe controller driver: - Add Toshiba Visconti PCIe host controller driver (Nobuhiro Iwamatsu) Xilinx NWL PCIe controller driver: - Enable PCIe reference clock via CCF (Hyun Kwon) Miscellaneous: - Convert sta2x11 from 'pci_' to 'dma_' API (Christophe JAILLET) - Fix pci_dev_str_match_path() alloc while atomic bug (used for kernel parameters that specify devices) (Dan Carpenter) - Remove pointless Precision Time Management warning when PTM is present but not enabled (Jakub Kicinski) - Remove surplus "break" statements (Krzysztof Wilczyński)" * tag 'pci-v5.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (132 commits) PCI: ibmphp: Fix double unmap of io_mem x86/PCI: sta2x11: switch from 'pci_' to 'dma_' API PCI/VPD: Use unaligned access helpers PCI/VPD: Clean up public VPD defines and inline functions cxgb4: Use pci_vpd_find_id_string() to find VPD ID string PCI/VPD: Add pci_vpd_find_id_string() PCI/VPD: Include post-processing in pci_vpd_find_tag() PCI/VPD: Stop exporting pci_vpd_find_info_keyword() PCI/VPD: Stop exporting pci_vpd_find_tag() PCI: Set dma-can-stall for HiSilicon chips PCI: rockchip-dwc: Add Rockchip RK356X host controller driver PCI: dwc: Remove surplus break statement after return PCI: artpec6: Remove local code block from switch statement PCI: artpec6: Remove surplus break statement after return MAINTAINERS: Add entries for Toshiba Visconti PCIe controller PCI: visconti: Add Toshiba Visconti PCIe host controller driver PCI/portdrv: Enable Bandwidth Notification only if port supports it PCI: Allow PASID on fake PCIe devices without TLP prefixes PCI: mediatek: Use PCI domain to handle ports detection PCI: mediatek: Add new method to get irq number ...
2021-08-27crypto: ccp - Add support for new CCP/PSP device IDJohn Allen1-0/+7
Add a new CCP/PSP PCI device ID and corresponding entry in the dev_vdata struct. Signed-off-by: John Allen <john.allen@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon - check _PS0 and _PR0 methodWeili Qian1-0/+4
To support runtime PM, use the function 'pci_set_power_state' to change the power state. Therefore, method _PS0 or _PR0 needs to be filled by platform. So check whether the method is supported, if not, print a prompt information. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon - change parameter passing of debugfs functionWeili Qian3-36/+20
To avoid repeatedly obtaining 'qm' from 'filp', parameter passing of debugfs function directly use 'qm' instead of 'filp'. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon - support runtime PM for accelerator deviceWeili Qian5-30/+297
Add runtime PM support for Kunpeng930 accelerator device. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon - add runtime PM opsWeili Qian2-0/+120
Accelerator devices support runtime PM to reduce power consumption. This patch adds the runtime PM suspend/resume callbacks to the accelerator devices. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon - using 'debugfs_create_file' instead of ↵Weili Qian5-27/+81
'debugfs_create_regset32' The accelerator devices support runtime PM, when device is in suspended, an exception will occur if reading registers. Therefore, this patch uses 'debugfs_create_file' instead of 'debugfs_create_regset32' to create debugfs file, and then the driver can get the device status before reading the register. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon/sec - modify the hardware endian configurationKai Ye2-27/+9
When the endian configuration of the hardware is abnormal, it will cause the SEC engine is faulty that reports empty message. And it will affect the normal function of the hardware. Currently the soft configuration method can't restore the faulty device. The endian needs to be configured according to the system properties. So fix it. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon/sec - fix the abnormal exiting processKai Ye1-1/+2
Because the algs registration process has added a judgment. So need to add the judgment for the abnormal exiting process. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - store vf.compatible flagGiovanni Cabiddu1-1/+3
If the VF is newer than the PF, it decides whether it is compatible or not. In case it is compatible, store that information in the vf.compatible flag in the accel_dev structure. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Suggested-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - do not export adf_iov_putmsg()Giovanni Cabiddu1-1/+0
The function adf_iov_putmsg() is only used inside the intel_qat module therefore should not be exported. Remove EXPORT_SYMBOL for the function adf_iov_putmsg(). Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - flush vf workqueue at driver removalAhsan Atta5-0/+33
There is a race condition during shutdown in adf_disable_sriov() where both the PF and the VF drivers are loaded on the host system. The PF notifies a VF with a "RESTARTING" message due to which the VF starts an asynchronous worker to stop and shutdown itself. At the same time the PF calls pci_disable_sriov() which invokes the remove() routine on the VF device driver triggering the shutdown flow again. This change fixes the problem by ensuring that the VF flushes the worker that performs stop()/shutdown() before these two functions are called in the remove(). To make sure that no additional PV/VF messages are processed by the VF, interrupts are disabled before flushing the workqueue. Signed-off-by: Ahsan Atta <ahsan.atta@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - remove the unnecessary get_vintmsk_offset()Marco Chiappero14-44/+2
All QAT GEN2 devices share the same register offset for masking interrupts, so they don't need any complex device specific infrastructure. Remove this function in favor of a constant in order to simplify the code. Also, future generations may require a more complex device specific handling, making the current approach obsolete anyway. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - fix naming of PF/VF enable functionsMarco Chiappero9-13/+13
Currently all the functions related to the activation of the PFVF protocol, both on PF and VF, include the direction specific "vf2pf" name. Replace the existing naming schema with: - a direction agnostic naming, that applies to both PF and VF, for the function pointer ("pfvf") - a direction specific naming schema for the implementations ("pf2vf" or "vf2pf") In particular this patch renames: - adf_pf_enable_vf2pf_comms() in adf_enable_pf2vf_comms() - enable_vf2pf_comms() in enable_pfvf_comms() Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - complete all the init steps before service notificationMarco Chiappero1-4/+6
Make sure all the steps in the initialization sequence are complete before any completion event notification. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - move IO virtualization functionsGiovanni Cabiddu4-15/+17
Move IOV functions at the end of hw_data so that PFVF functions related functions are group together. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - fix naming for init/shutdown VF to PF notificationsMarco Chiappero5-16/+16
At start and shutdown, VFs notify the PF about their state. These notifications are carried out through a message exchange using the PFVF protocol. Function names lead to believe they do perform init or shutdown logic. This is to fix the naming to better reflect their purpose. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - protect interrupt mask CSRs with a spinlockKanchana Velusamy7-4/+41
In the PF interrupt handler, the interrupt is disabled for a set of VFs by writing to the interrupt source mask register, ERRMSK. The interrupt is re-enabled in the bottom half handler by writing to the same CSR. This is done through the functions enable_vf2pf_interrupts() and disable_vf2pf_interrupts() which perform a read-modify-write operation on the ERRMSK registers to mask and unmask the source of interrupt. There can be a race condition where the top half handler for one VF interrupt runs just as the bottom half for another VF is about to re-enable the interrupt. Depending on whether the top or bottom half updates the CSR first, this would result either in a spurious interrupt or in the interrupt not being re-enabled. This patch protects the access of ERRMSK with a spinlock. The functions adf_enable_vf2pf_interrupts() and adf_disable_vf2pf_interrupts() have been changed to acquire a spin lock before accessing and modifying the ERRMSK registers. These functions use spin_lock_irqsave() to disable IRQs and avoid potential deadlocks. In addition, the function adf_disable_vf2pf_interrupts_irq() has been added. This uses spin_lock() and it is meant to be used in the top half only. Signed-off-by: Kanchana Velusamy <kanchanax.velusamy@intel.com> Co-developed-by: Marco Chiappero <marco.chiappero@intel.com> Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - move pf2vf interrupt [en|dis]able to adf_vf_isr.cMarco Chiappero2-20/+20
Interrupt code to enable interrupts from PF does not belong to the protocol code, so move it to the interrupt handling specific file for better code organization. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - fix reuse of completion variableMarco Chiappero1-0/+2
Use reinit_completion() to set to a clean state a completion variable, used to coordinate the VF to PF request-response flow, before every new VF request. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - remove intermediate tasklet for vf2pfSvyatoslav Pankratov4-13/+5
The PF driver uses the tasklet vf2pf_bh_tasklet to schedule a workqueue to handle the vf2vf protocol (pf2vf_resp_wq). Since the tasklet is only used to schedule the workqueue, this patch removes it and schedules the pf2vf_resp_wq workqueue directly for the top half. Signed-off-by: Svyatoslav Pankratov <svyatoslav.pankratov@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Marco Chiappero <marco.chiappero@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - rename compatibility version definitionMarco Chiappero9-17/+17
Rename ADF_PFVF_COMPATIBILITY_VERSION in ADF_PFVF_COMPAT_THIS_VERSION since it is used to indicate the current version of the PFVF protocol. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: qat - prevent spurious MSI interrupt in PFMarco Chiappero2-7/+20
There is a chance that the PFVF handler, adf_vf2pf_req_hndl(), runs twice for the same request when multiple interrupts come simultaneously from different VFs. Since the source VF is identified by a positional bit set in the ERRSOU registers and that is not cleared until the bottom half completes, new top halves from other VFs may reschedule a second bottom half for previous interrupts. This patch solves the problem in the ISR handler by not considering sources with already disabled interrupts (and processing pending), as set in the ERRMSK registers. Also, move some definitions where actually needed. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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