summaryrefslogtreecommitdiff
path: root/drivers/crypto
AgeCommit message (Collapse)AuthorFilesLines
2021-06-17crypto: hisilicon/qm - add the "alg_qos" file nodeKai Ye1-129/+155
1. Just move the code as needed. 2. Add the "alg_qos" file node in the qm debug sysfs. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-17crypto: hisilicon/qm - supports writing QoS int the hostKai Ye2-2/+310
Based on the Token bucket algorithm. The HAC driver supports to configure each function's QoS in the host. The driver supports writing QoS by the debugfs node that named "alg_qos". The qos value is 1~1000. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-17crypto: ccp - Use list_move_tail instead of list_del/list_add_tail in ↵Baokun Li1-2/+1
ccp-dmaengine.c Using list_move_tail() instead of list_del() + list_add_tail() in ccp-dmaengine.c. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Baokun Li <libaokun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-17crypto: marvell/cesa - change FPGA indirect article to anTom Rix1-1/+1
Change use of 'a fpga' to 'an fpga' Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: cavium/nitrox - Fix an error rhandling path in 'nitrox_probe()'Christophe JAILLET1-10/+8
If an error occurs after a successful 'ioremap()' call, it must be undone by a corresponding 'iounmap()' call, as already done in the remove function. Add a 'pf_sw_fail' label in the error handling path and add the missing 'iounmap()'. While at it, also add a 'flr_fail' label in the error handling path and use it to avoid some code duplication. Fixes: 14fa93cdcd9b ("crypto: cavium - Add support for CNN55XX adapters.") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: hisilicon/sec - modify the SEC request structureKai Ye2-19/+22
Modify the SEC request structure, combines two common parameters of the SEC request into one parameter. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: hisilicon/sec - add hardware integrity check value processKai Ye2-34/+48
Use hardware integrity check value process instead of soft verify process when doing aead decryption. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: hisilicon/sec - add fallback tfm supporting for aeadsKai Ye2-5/+94
Add fallback tfm supporting for hisi_sec driver. Due to the Kunpeng920's CCM/GCM algorithm not supports 0 byte src length. So the driver needs to setting the soft fallback aead tfm. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: hisilicon/sec - add new algorithm mode for AEADKai Ye3-34/+345
Add new algorithm mode for AEAD: CCM(AES), GCM(AES), CCM(SM4), GCM(SM4). Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: qce - fix error return code in qce_skcipher_async_req_handle()Wei Yongjun1-2/+6
Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: 1339a7c3ba05 ("crypto: qce: skcipher: Fix incorrect sg count for dma transfers") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: sl3516 - Add sl3516 crypto engineCorentin Labbe7-0/+1353
The cortina/gemini SL3516 SoC has a crypto IP name either (crypto engine/crypto acceleration engine in the datasheet). It support many algorithms like [AES|DES|3DES][ECB|CBC], SHA1, MD5 and some HMAC. This patch adds the core files and support for ecb(aes) and the RNG. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: omap-sham - Fix PM reference leak in omap sham opsZhang Qilong1-2/+2
pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to putting operation will result in reference leak here. We fix it by replacing it with pm_runtime_resume_and_get to keep usage counter balanced. Fixes: 604c31039dae4 ("crypto: omap-sham - Check for return value from pm_runtime_get_sync") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: omap-des - using pm_runtime_resume_and_get instead of ↵Zhang Qilong1-6/+3
pm_runtime_get_sync Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: nitrox - fix unchecked variable in nitrox_register_interruptsTong Tiangen1-0/+4
Function nitrox_register_interrupts leaves variable 'nr_vecs' unchecked, which would be use as kcalloc parameter later. Fixes: 5155e118dda9 ("crypto: cavium/nitrox - use pci_alloc_irq_vectors() while enabling MSI-X.") Signed-off-by: Tong Tiangen <tongtiangen@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/qm - update reset flowWeili Qian1-17/+262
This patch updates the reset flow based on PF/VF communications. VFs will be stopped after receiving reset message from PF, and wait for reset finish to restart VFs. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/qm - add callback to support communicationWeili Qian1-27/+190
This patch adds 'ping_all_vfs' callback that supports pf send message to all vfs and 'ping_pf' callback that supports vf send message to pf. After receiving the interrupt, the communication destination gets the message by sending mailbox. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/qm - enable PF and VFs communicationWeili Qian2-8/+106
Kunpeng930 hardware supports the communication between PF and VFs. This patch enables communication between PF and VFs by writing hardware registers, and requests an irq for communication. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/qm - adjust reset interfaceWeili Qian1-51/+89
Kunpeng930 hardware supports PF/VF communications. When the device is reset, PF can send message to VF to stop function and restart function. This patch adjusts the reset interface to support sending message through PF/VF communication. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/hpre - register ecdh NIST P384Hui Tang1-4/+52
Register ecdh NIST P384 curve and add the tfm initialization. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/hpre - add check before gx modulo pHui Tang1-1/+5
The result of gx modulo p is zero if gx is equal to p, so return error immediately if gx is equal to p. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/hpre - fix ecdh self test issueHui Tang1-0/+34
When the key length is zero, use stdrng to generate private key to pass the crypto ecdh-nist-p256 self test on vector 2. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - fixup 3des minimum key size declarationKai Ye1-2/+2
Fixup the 3des algorithm minimum key size declaration. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - add fallback tfm supporting for XTS modeKai Ye2-3/+86
Add fallback tfm supporting for hisi_sec driver. Due to the hardware not supports 192bit key length when using XTS mode. So the driver needs to setting the soft fallback skcipher tfm for user. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - add new skcipher mode for SECKai Ye2-12/+94
Add new skcipher algorithms for Kunpeng930 SEC: OFB(AES), CFB(AES), CTR(AES), OFB(SM4), CFB(SM4), CTR(SM4). Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - driver adapt to new SQEKai Ye3-43/+256
Due to Kunpeng930 adds new SQE data structure, the SEC driver needs to be upgraded. It mainly includes bd parsing process and bd filling process. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - add new type of SQEKai Ye2-1/+178
Add new type of sqe for Kunpeng930, which is the next generation of SEC accelerator hardware. The hardware adds a new SQE data structure. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: octeontx2 - enable and handle ME interruptsSrujana Challa1-23/+95
Adds master enable (ME) interrupt handler in PF. Upon receiving ME interrupt for a VF, PF clears it's transaction pending bit. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: octeontx2 - add support for CPT operations on CN10KSrujana Challa9-22/+134
CPT result format had changed for CN10K HW to accommodate more fields. This patch adds support to use new result format and new LMTST lines for CPT operations on CN10K platform. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: octeontx2 - add support to map LMTST region for CN10KSrujana Challa7-3/+86
On CN10K platform transmit/receive buffer alloc and free from/to hardware had changed to support burst operation. Whereas pervious silicon's only support single buffer free at a time. To Support the same firmware allocates a DRAM region for each PF/VF for storing LMTLINES. These LMTLINES are used to send CPT commands to HW. PF/VF LMTST region is accessed via BAR4. PFs LMTST region is followed by its VFs mbox memory. The size of region varies from 2KB to 256KB based on number of LMTLINES configured. This patch adds support for mapping of PF/VF LMTST region. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: octeontx2 - Add mailbox support for CN10KSrujana Challa8-33/+129
Mailbox region configuration has some changes on CN10K platform from OcteonTX2(CN9XX) platform. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. This patch changes mbox initialization to support both CN9XX and CN10K platform. This patch also removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: ixp4xx - Add device tree supportLinus Walleij1-28/+79
This makes the IXP4xx driver probe from the device tree and retrieve the NPE and two queue manager handled used to process crypto from the device tree. As the crypto engine is topologically a part of the NPE hardware, we augment the NPE driver to spawn the crypto engine as a child. The platform data probe path is going away in due time, for now it is an isolated else clause. Cc: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: ixp4xx - convert to platform driverArnd Bergmann1-24/+13
The ixp4xx_crypto driver traditionally registers a bare platform device without attaching it to a driver, and detects the hardware at module init time by reading an SoC specific hardware register. Change this to the conventional method of registering the platform device from the platform code itself when the device is present, turning the module_init/module_exit functions into probe/release driver callbacks. This enables compile-testing as well as potentially having ixp4xx coexist with other ARMv5 platforms in the same kernel in the future. Cc: Corentin Labbe <clabbe@baylibre.com> Tested-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon - switch to memdup_user_nul()Zou Wei1-10/+3
Use memdup_user_nul() helper instead of open-coding to simplify the code. v1-->v2: fixed patch title error v2-->v3: return the actual error Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: hisilicon/qm - support address prefetchingLongfang Liu5-0/+182
Kunpeng930 hardware supports address prefetching to improve performance before doing tasks in SVA scenario. This patch enables this function in device initialization by writing hardware registers. In the process of reset, address prefetching is disabled to avoid the failure of interaction between accelerator device and SMMU. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: hisilicon/qm - add MSI detection steps on Kunpeng930Weili Qian1-24/+100
Compared with Kunpeng920, Kunpeng930 adds MSI configuration steps to wait for the interrupt to be emptied. In order to be compatible with the kunpeng920 driver, 'set_msi' callback is added in 'hisi_qm_hw_ops' to configure hardware register. Call 'set_msi' to disable or enable MSI during reset. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: hisilicon/qm - fix the process of VF's list addingKai Ye1-8/+8
If Kunpeng 920 enabled the sva mode, the "qm alg register" process will return directly. So the list of VF wasn't added to QM list. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: hisilicon/qm - add dfx log if not use hardware crypto algsKai Ye1-2/+5
Add print information necessary if not use hardware crypto algs. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: qce - Fix inconsistent indentingJiapeng Chong1-1/+1
Eliminate the follow smatch warning: drivers/crypto/qce/aead.c:85 qce_aead_done() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: nx - Fix typo in commentShaokun Zhang1-2/+2
Fix typo '@workmem' -> '@wmem'. Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: qce: skcipher: Fix incorrect sg count for dma transfersThara Gopinath1-7/+8
Use the sg count returned by dma_map_sg to call into dmaengine_prep_slave_sg rather than using the original sg count. dma_map_sg can merge consecutive sglist entries, thus making the original sg count wrong. This is a fix for memory coruption issues observed while testing encryption/decryption of large messages using libkcapi framework. Patch has been tested further by running full suite of tcrypt.ko tests including fuzz tests. Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: ccp: ccp-dev: Fix a little doc-rotLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): drivers/crypto/ccp/ccp-dev.c:476: warning: Function parameter or member 'sp' not described in 'ccp_alloc_struct' drivers/crypto/ccp/ccp-dev.c:476: warning: Excess function parameter 'dev' description in 'ccp_alloc_struct' drivers/crypto/ccp/ccp-dev.c:476: warning: Function parameter or member 'sp' not described in 'ccp_alloc_struct' drivers/crypto/ccp/ccp-dev.c:476: warning: Excess function parameter 'dev' description in 'ccp_alloc_struct' Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: John Allen <john.allen@amd.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: Gary R Hook <gary.hook@amd.com> Cc: linux-crypto@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: nx: nx-aes-gcm: Kernel-doc formatting should not be used for headersLee Jones1-13/+11
Fixes the following W=1 kernel build warning(s): drivers/crypto/nx/nx-aes-gcm.c:26: warning: Function parameter or member 'tfm' not described in 'gcm_aes_nx_set_key' drivers/crypto/nx/nx-aes-gcm.c:26: warning: Function parameter or member 'in_key' not described in 'gcm_aes_nx_set_key' drivers/crypto/nx/nx-aes-gcm.c:26: warning: Function parameter or member 'key_len' not described in 'gcm_aes_nx_set_key' drivers/crypto/nx/nx-aes-gcm.c:26: warning: expecting prototype for Nest Accelerators driver(). Prototype was for gcm_aes_nx_set_key() instead drivers/crypto/nx/nx-aes-ecb.c:24: warning: Function parameter or member 'tfm' not described in 'ecb_aes_nx_set_key' drivers/crypto/nx/nx-aes-ecb.c:24: warning: Function parameter or member 'in_key' not described in 'ecb_aes_nx_set_key' drivers/crypto/nx/nx-aes-ecb.c:24: warning: Function parameter or member 'key_len' not described in 'ecb_aes_nx_set_key' drivers/crypto/nx/nx-aes-ecb.c:24: warning: expecting prototype for Nest Accelerators driver(). Prototype was for ecb_aes_nx_set_key() instead drivers/crypto/nx/nx-aes-ccm.c:26: warning: Function parameter or member 'tfm' not described in 'ccm_aes_nx_set_key' drivers/crypto/nx/nx-aes-ccm.c:26: warning: Function parameter or member 'in_key' not described in 'ccm_aes_nx_set_key' drivers/crypto/nx/nx-aes-ccm.c:26: warning: Function parameter or member 'key_len' not described in 'ccm_aes_nx_set_key' drivers/crypto/nx/nx-aes-ccm.c:26: warning: expecting prototype for Nest Accelerators driver(). Prototype was for ccm_aes_nx_set_key() instead drivers/crypto/nx/nx-aes-ctr.c:25: warning: Function parameter or member 'tfm' not described in 'ctr_aes_nx_set_key' drivers/crypto/nx/nx-aes-ctr.c:25: warning: Function parameter or member 'in_key' not described in 'ctr_aes_nx_set_key' drivers/crypto/nx/nx-aes-ctr.c:25: warning: Function parameter or member 'key_len' not described in 'ctr_aes_nx_set_key' drivers/crypto/nx/nx-aes-ctr.c:25: warning: expecting prototype for Nest Accelerators driver(). Prototype was for ctr_aes_nx_set_key() instead drivers/crypto/nx/nx-aes-xcbc.c:22: warning: cannot understand function prototype: 'struct xcbc_state ' drivers/crypto/nx/nx-sha256.c:21: warning: Function parameter or member 'tfm' not described in 'nx_crypto_ctx_sha256_init' drivers/crypto/nx/nx-sha256.c:21: warning: expecting prototype for SHA(). Prototype was for nx_crypto_ctx_sha256_init() instead drivers/crypto/nx/nx-sha512.c:20: warning: Function parameter or member 'tfm' not described in 'nx_crypto_ctx_sha512_init' drivers/crypto/nx/nx-sha512.c:20: warning: expecting prototype for SHA(). Prototype was for nx_crypto_ctx_sha512_init() instead drivers/crypto/nx/nx-842-pseries.c:280: warning: Function parameter or member 'wmem' not described in 'nx842_pseries_compress' drivers/crypto/nx/nx-842-pseries.c:280: warning: Excess function parameter 'wrkmem' description in 'nx842_pseries_compress' drivers/crypto/nx/nx-842-pseries.c:410: warning: Function parameter or member 'wmem' not described in 'nx842_pseries_decompress' drivers/crypto/nx/nx-842-pseries.c:410: warning: Excess function parameter 'wrkmem' description in 'nx842_pseries_decompress' drivers/crypto/nx/nx-842-pseries.c:523: warning: Function parameter or member 'devdata' not described in 'nx842_OF_set_defaults' drivers/crypto/nx/nx-842-pseries.c:548: warning: Function parameter or member 'prop' not described in 'nx842_OF_upd_status' drivers/crypto/nx/nx-842-pseries.c:582: warning: Function parameter or member 'devdata' not described in 'nx842_OF_upd_maxsglen' drivers/crypto/nx/nx-842-pseries.c:582: warning: Function parameter or member 'prop' not described in 'nx842_OF_upd_maxsglen' drivers/crypto/nx/nx-842-pseries.c:630: warning: Function parameter or member 'devdata' not described in 'nx842_OF_upd_maxsyncop' drivers/crypto/nx/nx-842-pseries.c:630: warning: Function parameter or member 'prop' not described in 'nx842_OF_upd_maxsyncop' drivers/crypto/nx/nx-842-pseries.c:692: warning: Cannot understand * drivers/crypto/nx/nx-842-pseries.c:825: warning: Function parameter or member 'data' not described in 'nx842_OF_notifier' drivers/crypto/nx/nx-842-pseries.c:825: warning: Excess function parameter 'update' description in 'nx842_OF_notifier' Cc: Haren Myneni <haren@us.ibm.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Robert Jennings <rcj@linux.vnet.ibm.com> Cc: Seth Jennings <sjenning@linux.vnet.ibm.com> Cc: linux-crypto@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: cavium: Fix a bunch of kernel-doc related issuesLee Jones6-13/+15
Fixes the following W=1 kernel build warning(s): drivers/crypto/cavium/nitrox/nitrox_main.c:41: warning: cannot understand function prototype: 'const struct pci_device_id nitrox_pci_tbl[] = ' drivers/crypto/cavium/nitrox/nitrox_main.c:73: warning: Function parameter or member 'ndev' not described in 'write_to_ucd_unit' drivers/crypto/cavium/nitrox/nitrox_main.c:73: warning: Function parameter or member 'ucode_size' not described in 'write_to_ucd_unit' drivers/crypto/cavium/nitrox/nitrox_main.c:73: warning: Function parameter or member 'ucode_data' not described in 'write_to_ucd_unit' drivers/crypto/cavium/nitrox/nitrox_main.c:73: warning: Function parameter or member 'block_num' not described in 'write_to_ucd_unit' drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:46: warning: Function parameter or member 'index' not described in 'incr_index' drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:46: warning: Function parameter or member 'count' not described in 'incr_index' drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:46: warning: Function parameter or member 'max' not described in 'incr_index' drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:46: warning: expecting prototype for Response codes from SE microcode(). Prototype was for incr_index() instead drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:287: warning: Function parameter or member 'cmdq' not described in 'post_se_instr' drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:381: warning: Function parameter or member 'callback' not described in 'nitrox_process_se_request' drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:381: warning: Function parameter or member 'cb_arg' not described in 'nitrox_process_se_request' drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:381: warning: expecting prototype for nitrox_se_request(). Prototype was for nitrox_process_se_request() instead drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:535: warning: Function parameter or member 'cmdq' not described in 'process_response_list' drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:535: warning: expecting prototype for process_request_list(). Prototype was for process_response_list() instead drivers/crypto/cavium/nitrox/nitrox_reqmgr.c:584: warning: Function parameter or member 'data' not described in 'pkt_slc_resp_tasklet' drivers/crypto/cavium/nitrox/nitrox_mbx.c:14: warning: cannot understand function prototype: 'enum mbx_msg_type ' drivers/crypto/cavium/nitrox/nitrox_mbx.c:24: warning: cannot understand function prototype: 'enum mbx_msg_opcode ' drivers/crypto/cavium/nitrox/nitrox_skcipher.c:26: warning: cannot understand function prototype: 'const struct nitrox_cipher flexi_cipher_table[] = ' drivers/crypto/cavium/cpt/cptpf_main.c:411: warning: Function parameter or member 'cpt' not described in 'cpt_unload_microcode' drivers/crypto/cavium/cpt/cptpf_main.c:411: warning: expecting prototype for Ensure all cores are disengaged from all groups by(). Prototype was for cpt_unload_microcode() instead drivers/crypto/cavium/cpt/cptvf_reqmanager.c:17: warning: Function parameter or member 'q' not described in 'get_free_pending_entry' drivers/crypto/cavium/cpt/cptvf_reqmanager.c:17: warning: Function parameter or member 'qlen' not described in 'get_free_pending_entry' Cc: George Cherian <gcherian@marvell.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: linux-crypto@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: qce - Fix some error handling pathWei Yongjun1-3/+9
Fix to return negative error code from the error handling cases instead of 0. Fixes: 9363efb4181c ("crypto: qce - Add support for AEAD algorithms") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: qat - remove unused macro in FW loaderJack Xu1-1/+0
Remove the unused macro ICP_DH895XCC_PESRAM_BAR_SIZE in the firmware loader. This is to fix the following warning when compiling the driver using the clang compiler with CC=clang W=2: drivers/crypto/qat/qat_common/qat_uclo.c:345:9: warning: macro is not used [-Wunused-macros] Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Zhehui Xiang <zhehui.xiang@intel.com> Signed-off-by: Zhehui Xiang <zhehui.xiang@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: qat - check return code of qat_hal_rd_rel_reg()Jack Xu1-1/+5
Check the return code of the function qat_hal_rd_rel_reg() and return it to the caller. This is to fix the following warning when compiling the driver with clang scan-build: drivers/crypto/qat/qat_common/qat_hal.c:1436:2: warning: 6th function call argument is an uninitialized value Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Zhehui Xiang <zhehui.xiang@intel.com> Signed-off-by: Zhehui Xiang <zhehui.xiang@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: qat - report an error if MMP file size is too largeJack Xu1-4/+2
Change the return status to error if MMP file size is too large so the driver load fails early if a large MMP firmware is loaded. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Zhehui Xiang <zhehui.xiang@intel.com> Signed-off-by: Zhehui Xiang <zhehui.xiang@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: qat - check MMP size before writing to the SRAMJack Xu3-6/+6
Change "sram_visible" to "mmp_sram_size" and compare it with the MMP size to prevent an overly large MMP file being written to SRAM. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Zhehui Xiang <zhehui.xiang@intel.com> Signed-off-by: Zhehui Xiang <zhehui.xiang@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: qat - return error when failing to map FWJack Xu1-1/+2
Save the return value of qat_uclo_map_auth_fw() function so that the function qat_uclo_wr_mimage() could return the correct value. This way, the procedure of adf_gen2_ae_fw_load() function could stop and exit properly by checking the return value of qat_uclo_wr_mimage(). Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Zhehui Xiang <zhehui.xiang@intel.com> Signed-off-by: Zhehui Xiang <zhehui.xiang@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-23crypto: ccp - Fix a resource leak in an error handling pathChristophe JAILLET1-2/+4
If an error occurs after calling 'sp_get_irqs()', 'sp_free_irqs()' must be called as already done in the error handling path. Fixes: f4d18d656f88 ("crypto: ccp - Abstract interrupt registeration") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: John Allen <john.allen@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-17 11:52:40 +0300