starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-08-20	RISC-V: Remove CLINT related code from timer and arch	Anup Patel	1	-15/+2
2020-06-10	clocksource/drivers/timer-riscv: Use per-CPU timer interrupt	Anup Patel	1	-3/+40
2020-01-05	clocksource: riscv: add notrace to riscv_sched_clock	Zong Li	1	-1/+1
2019-11-14	riscv: add support for MMIO access to the timer registers	Christoph Hellwig	1	-4/+19
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-4/+4
2019-09-05	riscv: don't use the rdtime(h) pseudo-instructions	Christoph Hellwig	1	-13/+4
2019-08-07	RISC-V: Remove per cpu clocksource	Atish Patra	1	-4/+2
2019-03-23	clocksource/drivers/riscv: Fix clocksource mask	Atish Patra	1	-3/+2
2019-02-23	clocksource/drivers/riscv: Add required checks during clock source init	Atish Patra	1	-3/+20
2018-12-19	clocksource/drivers/riscv: Change name riscv_timer to timer-riscv	Daniel Lezcano	1	-0/+118