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2024-07-03clk: disable clk gate tests for s390Audra Mitchell1-0/+1
Currently clk-gate tests for s390 fail as the tests create a pretend clk-gate and use a "fake_reg" to emulate the expected behavior of the clk_gate->reg. I added some debug statements to the driver and noticed that the reg changes after initialization to -1, which is coming from an error coming from zpci_load(). This is likely because the test is using fake iomem and the s390 architecture likely isn't designed to handle that. Turn off the clk-gate tests for s390 for now as there is no clear work around for this problem as discussed in upstream conversation [1]. [1] https://lore.kernel.org/all/301cd41e6283c12ac67fb8c0f8d5c929.sboyd@kernel.org/T/#t Signed-off-by: Audra Mitchell <audra@redhat.com> Link: https://lore.kernel.org/r/20240702125539.524489-1-audra@redhat.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-07-02Merge tag 'qcom-clk-fixes-for-6.10' of ↵Stephen Boyd4-11/+14
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes Pull Qualcomm clk driver fixes from Bjorn Andersson: - Correct the Stromer Plus PLL set_rate to explicitly set ALPHA_EN bit and remove unnecessary upper parts of CONFIG_CTL values. - Mark the recently added IPQ9574 GCC crypto clocks BRANCH_HALT_VOTED, to address stuck clock warnings. - Fix the GPLL6 and GPLL7 parents on SM6350 to avoid issues with these reportedly running at ~25GHz. * tag 'qcom-clk-fixes-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: gcc-ipq9574: Add BRANCH_HALT_VOTED flag clk: qcom: apss-ipq-pll: remove 'config_ctl_hi_val' from Stromer pll configs clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents
2024-07-02clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocksAbel Vesa1-22/+22
In case of all pipe clocks, there is a QMP PHY clock that is feeding them. If, for whatever reason, the clock from the PHY is not enabled, halt bit will not get set, and the clock controller driver will assume the clock is stuck in a specific state. The way this is supposed to be properly fixed is to defer the checking of the halt bit until after the PHY clock has been initialized, but doing so complicates the clock controller driver. In fact, since these pipe clocks are consumed by the PHY, while the PHY is also the one providing the source, if clock gets stuck, the PHY driver would be to blame. So instead of checking the halt bit in here, just skip it and assume the PHY driver is handling the source clock correctly. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240628-x1e80100-clk-gcc-fix-halt-check-for-usb-phy-pipe-clks-v2-1-db3be54b1143@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-01clk: mediatek: mt8183: Only enable runtime PM on mt8183-mfgcfgPin-yen Lin3-10/+17
Commit 2f7b1d8b5505 ("clk: mediatek: Do a runtime PM get on controllers during probe") enabled runtime PM for all mediatek clock controllers, but this introduced an issue on the resume path. If a device resumes earlier than the clock controller and calls clk_prepare() when runtime PM is enabled on the controller, it will end up calling clk_pm_runtime_get(). But the subsequent pm_runtime_resume_and_get() call will fail because the runtime PM is temporarily disabled during suspend. To workaround this, introduce a need_runtime_pm flag and only enable it on mt8183-mfgcfg, which is the driver that observed deadlock previously. Hopefully mt8183-cfgcfg won't run into the issue at the resume stage because the GPU should have stopped rendering before the system calls suspend. Fixes: 2f7b1d8b5505 ("clk: mediatek: Do a runtime PM get on controllers during probe") Signed-off-by: Pin-yen Lin <treapking@chromium.org> Link: https://lore.kernel.org/r/20240613120357.1043342-1-treapking@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-07-01Merge tag 'sunxi-clk-fixes-for-6.10' of ↵Stephen Boyd1-6/+12
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull one Allwinner SoC clk driver fix for 6.10 - Fix min/max rate clamping that caused a regression back in 6.9 * tag 'sunxi-clk-fixes-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: common: Don't call hw_to_ccu_common on hw without common
2024-07-01clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as criticalPeter Griffin1-1/+1
The system hangs on poweroff when this UFS clock is turned off, meaning the system never powers down. For the moment mark the clock as critical. Reviewed-by: Will McVicker <willmcvicker@google.com> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240628223506.1237523-5-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-06-30clk: sunxi-ng: common: Don't call hw_to_ccu_common on hw without commonFrank Oltmanns1-6/+12
In order to set the rate range of a hw sunxi_ccu_probe calls hw_to_ccu_common() assuming all entries in desc->ccu_clks are contained in a ccu_common struct. This assumption is incorrect and, in consequence, causes invalid pointer de-references. Remove the faulty call. Instead, add one more loop that iterates over the ccu_clks and sets the rate range, if required. Fixes: b914ec33b391 ("clk: sunxi-ng: common: Support minimum and maximum rate") Reported-by: Robert J. Pafford <pafford.9@buckeyemail.osu.edu> Closes: https://lore.kernel.org/lkml/DM6PR01MB58047C810DDD5D0AE397CADFF7C22@DM6PR01MB5804.prod.exchangelabs.com/ Cc: stable@vger.kernel.org Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Tested-by: Robert J. Pafford <pafford.9@buckeyemail.osu.edu> Link: https://lore.kernel.org/r/20240623-sunxi-ng_fix_common_probe-v1-1-7c97e32824a1@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-06-27clk: rockchip: rk3188: Drop CLK_NR_CLKS usageJohan Jonker1-4/+14
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/1cd309fa-a4d3-4283-aa47-1330a40448a7@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-27clk: renesas: r9a08g045: Add clock, reset and power domain support for I2CClaudiu Beznea1-0/+20
Add clock, reset and power domain support for the I2C channels available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625121358.590547-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-27clk: renesas: r8a779h0: Add Audio clocksKuninori Morimoto1-0/+2
Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/87h6djkxf2.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-27clk: renesas: r9a08g045: Add clock, reset and power domain support for the ↵Claudiu Beznea1-0/+6
VBATTB IP The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-26clk: qcom: gcc-ipq6018: update sdcc max clock frequencyChukun Pan1-1/+1
The mmc controller of the IPQ6018 does not support HS400 mode. So adjust the maximum clock frequency of sdcc to 200 MHz (HS200). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-26Merge branch '20240602114439.1611-1-quic_jkona@quicinc.com' into clk-for-6.11Bjorn Andersson4-5/+3751
Merge SM8650 video and camera clock drivers through topic branch, to make available the DeviceTree binding includes to the DeviceTree source branches as well.
2024-06-26clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driverJagadeesh Kona3-0/+3600
Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8650 platform. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-8-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-26clk: qcom: videocc-sm8550: Add SM8650 video clock controllerJagadeesh Kona1-4/+149
Add support to the SM8650 video clock controller by extending the SM8550 video clock controller, which is mostly identical but SM8650 has few additional clocks and minor differences. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-5-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-26clk: qcom: videocc-sm8550: Add support for videocc XO clk aresJagadeesh Kona1-1/+2
Add support for videocc XO clk ares for consumer drivers to be able to request this reset. Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-4-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-24clk: renesas: Drop "Renesas" from individual driver descriptionsGeert Uytterhoeven1-2/+2
All configuration options are under the big "Renesas SoC clock support" umbrella, so there is no reason to repeat this for each driver. Hence drop "Renesas" from the few that do. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/185323de4d38b9b599775c1b64ce4171551b98d5.1718177124.git.geert+renesas@glider.be
2024-06-24clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in commentsGeert Uytterhoeven1-3/+3
The multipliers for PLL2 and PLL4 as listed in the comments for the cpg_pll_configs[] array are incorrect. Fix them. Note that the actual values in the tables were correct. Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M") Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be
2024-06-24clk: imx: composite-7ulp: Use NULL instead of 0Peng Fan1-1/+1
Address the sparse warnings " sparse warnings: (new ones prefixed by >>) >> drivers/clk/imx/clk-composite-7ulp.c:85:24: sparse: sparse: Using plain integer as NULL pointer " Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406220536.JnAncjqz-lkp@intel.com/ Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240624024351.488492-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-24clk: imx: add missing MODULE_DESCRIPTION() macrosJeff Johnson2-0/+2
make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/mxc-clk.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/clk-imxrt1050.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240602-md-clk-imx-v1-1-5c6d240f6fab@quicinc.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-24clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC'sTaniya Das1-0/+6
Update wait_val fields as per the default hardware values of the GDSC as otherwise it would lead to GDSC FSM state stuck causing power on/off failures of the GSDC. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-6-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-24clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disableTaniya Das1-4/+4
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Also gpu_cc_cb_clk is recommended to be kept always ON, hence use clk_branch2_aon_ops to keep the clock always ON. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-5-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-24clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flagsTaniya Das1-16/+11
The GPU clocks/GDSCs have been marked critical from the clock driver but the GPU driver votes on these resources as per the HW requirement. In the case where these clocks & GDSCs are left enabled, would have power impact and also cause GPU stability/corruptions. Fix the same by removing the CLK_IS_CRITICAL for clocks and ALWAYS_ON flags for the GPU GDSCs. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-4-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-24clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clkTaniya Das1-0/+3
Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-3-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-24clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flagsTaniya Das1-0/+40
Update the GDSC wait_val fields as per the default hardware values as otherwise they would lead to GDSC FSM state to be stuck and causing failures to power on/off. Also add the GDSC flags as applicable and add support to control PCIE GDSC's using collapse vote registers. Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-2-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-24clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocksTaniya Das1-109/+2
The UFS hw ctl clocks are not used by any consumers on SA8775P, and these clocks are not using the correct clock ops to manage the hw ctl of the branch clock, hence remove these clocks. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-1-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: qcom: gpucc-sm8350: Park RCG's clk source at XO during disableTaniya Das1-2/+3
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Fixes: 160758b05ab1 ("clk: qcom: add support for SM8350 GPUCC") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8350-HDK Link: https://lore.kernel.org/r/20240621-sm8350-gpucc-fixes-v1-1-22db60c7c5d3@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: rockchip: Switch to use kmemdup_array()Andy Shevchenko2-7/+6
Let the kememdup_array() take care about multiplication and possible overflows. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240606161028.2986587-3-andriy.shevchenko@linux.intel.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-23clk: rockchip: rk3128: Add HCLK_SFCAlex Bee1-0/+1
The SFC IP exists only in RK3128 version of the SoC, thus the clock gets added to rk3128_clk_branches. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20240606143401.32454-6-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-22clk: sunxi-ng: h616: Add clock/reset for GPADCChris Morgan2-1/+6
Add the GPADC required clock and reset which is used for the onboard GPADC. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20240605172049.231108-3-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-06-21clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rateMarek Vasut2-2/+6
The media_disp[12]_pix clock supply LCDIFv3 pixel clock output. These clocks are usually the only downstream clock from Video PLL on i.MX8MP. Allow these clocks to reconfigure the Video PLL, as that results in accurate pixel clock. If the Video PLL is not reconfigured, the pixel clock accuracy is low. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240531202648.277078-1-marex@denx.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: fracn-gppll: update rate tablePeng Fan1-0/+2
- Add 1039.5MHz clock for video PLL to fulfill the LVDS display 148.5MHz * 7 requirement - Add 800MHz clock for ARM PLL Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-16-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: imx8qxp: Parent should be initialized earlier than the clockPeng Fan1-3/+3
The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-15-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clkPeng Fan1-2/+2
The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: 91e916771de0 ("clk: imx: scu: remove legacy scu clock binding support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-14-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocksOliver F. Brown1-4/+20
The MIPI Pixel and PHY Reference can use the bypass clock as a source. The MIPI bypass clock is the Pixel clock from the Display controller via the pixel link. Using the pixel clock for the PHY reference allows the MIPI bit clock match the pixel rate exactly. The MIPI pixel clock is currently set to be source from the bypass clock in the SCFW. This patch allows the pixel clock parent to be set by the kernel in the event that the SCFW default clock parent may change in the future. Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com> Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-13-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: imx8qxp: Add LVDS bypass clocksPeng Fan1-9/+8
For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS clocks with imx_clk_scu2 as the parent needs to explicitly set. In order to make sure MIPI DSI works well after suspend/resume, the LVDS pixel and phy clocks must be initialized before the MIPI tx_esacpe and rx_escape clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all on the same MSLICE. They all share the same clock parent. So, setting the parent source or rate affects all of these clocks. In the LVDS use case the MIPI tx_escape and rx_escape are not saved and restored. So, LVDS works for either clock initialization order. For MIPI case, LVDS must be initialized first. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-12-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical oneJacky Bai1-1/+1
The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-11-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: imx8mn: add sai7_ipg_clk clock settingsAdrian Alonso1-0/+1
Add IMX8MN_CLK_SAI7_IPG clock entry. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-10-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7DPeng Fan1-1/+1
Add flag 'CLK_SET_RATE_PARENT' to 'IMX7D_LCDIF_PIXEL_ROOT_SRC' to propagate rate changes from LCDIF pixel clock to video PLL to provide more accurate clock rate for LCDIF pixel clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-9-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7DPeng Fan1-2/+2
For i.MX7D DRAM related mux clock, the clock source change should ONLY be done done in low level asm code without accessing DRAM, and then calling clk API to sync the HW clock status with clk tree, it should never touch real clock source switch via clk API, so CLK_SET_PARENT_GATE flag should NOT be added, otherwise, DRAM's clock parent will be disabled when DRAM is active, and system will hang. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: imx8mp: fix clock tree update of TF-A managed clocksZhipeng Wang1-2/+2
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. since commit 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: clk_set_parent(dram_apb_src, sys1_pll_40m);(busfreq-imx8mq.c) commit 926bf91248dd ("clk: imx8m: fix clock tree update of TF-A managed clocks") adds this method and enables 8mm, 8mn and 8mq. i.MX8MP also needs it. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Another reason to this patch is that powersave image BT music requires dram to be 400MTS, so clk_set_parent(dram_alt_src, sys1_pll_800m); is required. Without this patch, it will not succeed. Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Zhipeng Wang <zhipeng.wang_1@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-7-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: fracn-gppll: fix fractional part of PLL getting lostPengfei Li1-0/+4
Fractional part of PLL gets lost after re-enabling the PLL. the MFN can NOT be automatically loaded when doing frac PLL enable/disable, So when re-enable PLL, configure mfn explicitly. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: composite-7ulp: Check the PCC present bitYe Li1-0/+7
When some module is disabled by fuse, its PCC PR bit is default 0 and PCC is not operational. Any write to this PCC will cause SError. Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp") Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: composite-93: keep root clock on when mcore enabledJacky Bai1-7/+8
Previously we assumed that the root clock slice is enabled by default when kernel boot up. But the bootloader may disable the clocks before jump into kernel. The gate ops should be registered rather than NULL to make sure the disabled clock can be enabled when kernel boot up. Refine the code to skip disable the clock if mcore booted. Fixes: a740d7350ff7 ("clk: imx: imx93: add mcore_booted module paratemter") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Tested-by: Chancel Liu <chancel.liu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: composite-8m: Enable gate clk with mcore_bootedPeng Fan1-11/+42
Bootloader might disable some CCM ROOT Slices. So if mcore_booted set with display CCM ROOT disabled by Bootloader, kernel display BLK CTRL driver imx8m_blk_ctrl_driver_init may hang the system because the BUS clk is disabled. Add back gate ops, but with disable doing nothing, then the CCM ROOT will be enabled when used. Fixes: bb7e897b002a ("clk: imx8m: check mcore_booted before register clk") Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: imx6ul: fix default parent for enet*_ref_selSebastien Laveze1-2/+2
The clk_set_parent for "enet1_ref_sel" and "enet2_ref_sel" are incorrect, therefore the original requirements to have "enet_clk_ref" as output sourced by iMX ENET PLL as a default config is not met. Only "enet[1,2]_ref_125m" "enet[1,2]_ref_pad" are possible parents for "enet1_ref_sel" and "enet2_ref_sel". This was observed as a regression using a custom device tree which was expecting this default config. This can be fixed at the device tree level but having a default config matching the original behavior (before refclock mux) will avoid breaking existing configs. Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") Link: https://lore.kernel.org/lkml/20230306020226.GC143566@dragon/T/ Signed-off-by: Sebastien Laveze <slaveze@smartandconnective.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/20240528151434.227602-1-slaveze@smartandconnective.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpllShengjiu Wang1-2/+11
According to Reference Manual of i.MX8MP The parent clock of "earc_phy" is "sai_pll_out_div2", The parent clock of "audpll" is "osc_24m". Add CLK_GATE_PARENT() macro for usage of specifying parent clock. Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1718350923-21392-6-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocksShengjiu Wang1-4/+6
Add CLK_SET_RATE_PARENT flags that when the device driver sets the child clock rate, parent clock frequency can be refined accordingly. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1718350923-21392-5-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-06-21clk: qcom: nsscc-qca8k: Fix the MDIO functions undefined issueLuo Jie1-1/+1
The clock controller driver of QCA8K depends on MDIO_BUS because of mdio_module_driver used to register the driver. This patch fixes the following undefined symbols. ERROR: modpost: "mdio_driver_register" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "mdio_driver_unregister" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_write" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_read" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406161634.B27sOs8B-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202406162047.QkUMa2fG-lkp@intel.com/ Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240617093806.3461165-1-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-21clk: qcom: select right config in CLK_QCM2290_GPUCC definitionLukas Bulwahn1-1/+1
Commit 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver") adds the config CLK_QCM2290_GPUCC, which intends to select the support for the QCM2290 Global Clock Controller. It however selects the non-existing config CLK_QCM2290_GCC, whereas the config for the QCM2290 Global Clock Controller is named QCM_GCC_2290. Adjust the config to the intended one. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com> Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240620201431.93254-1-lukas.bulwahn@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-17 01:27:47 +0300