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2023-12-18clk: si5351: allow PLLs to be adjusted without resetAlvin Šipraga1-3/+44
Introduce a new PLL reset mode flag which controls whether or not to reset a PLL after adjusting its rate. The mode can be configured through platform data or device tree. Since commit 6dc669a22c77 ("clk: si5351: Add PLL soft reset"), the driver unconditionally resets a PLL whenever its rate is adjusted. The rationale was that a PLL reset was required to get three outputs working at the same time. Before this change, the driver never reset the PLLs. Commit b26ff127c52c ("clk: si5351: Apply PLL soft reset before enabling the outputs") subsequently introduced an option to reset the PLL when enabling a clock output that sourced it. Here, the rationale was that this is required to get a deterministic phase relationship between multiple output clocks. This clearly shows that it is useful to reset the PLLs in applications where multiple clock outputs are used. However, the Si5351 also allows for glitch-free rate adjustment of its PLLs if one avoids resetting the PLL. In our audio application where a single Si5351 clock output is used to supply a runtime adjustable bit clock, this unconditional PLL reset behaviour introduces unwanted glitches in the clock output. It would appear that the problem being solved in the former commit may be solved by using the optional device tree property introduced in the latter commit, obviating the need for an unconditional PLL reset after rate adjustment. But it's not OK to break the default behaviour of the driver, and it cannot be assumed that all device trees are using the property introduced in the latter commit. Hence, the new behaviour is made opt-in. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Jacob Siverskog <jacob@teenage.engineering> Cc: Sergej Sawazki <sergej@taudac.com> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lore.kernel.org/r/20231124-alvin-clk-si5351-no-pll-reset-v6-3-69b82311cb90@bang-olufsen.dk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: si5341: fix an error code problem in si5341_output_clk_set_rateSu Hui1-3/+1
regmap_bulk_write() return zero or negative error code, return the value of regmap_bulk_write() rather than '0'. Fixes: 3044a860fd09 ("clk: Add Si5341/Si5340 driver") Acked-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Su Hui <suhui@nfschina.com> Link: https://lore.kernel.org/r/20231101031633.996124-1-suhui@nfschina.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: versaclock3: Drop ret variableBiju Das1-19/+11
Drop ret variable from vc3_clk_mux_determine_rate(). While at it, return the value returned by regmap_* wherever possible instead of returning 0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-6-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: versaclock3: Add missing space between ')' and '{'Biju Das1-22/+22
Add missing space between ')' and '{' for hw.init initialization. While at it, update the macro VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a->0xa. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-5-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: versaclock3: Use u8 return type for get_parent() callbackBiju Das1-3/+3
The return type of get_parent() member in struct clk_ops is u8. Use same return type for corresponding callback function as well. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-4-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: versaclock3: Avoid unnecessary paddingBiju Das1-3/+3
Move long/pointer variables at the beginning of struct to avoid unnecessary padding. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-3-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: versaclock3: Update vc3_get_div() to avoid divide by zeroBiju Das1-1/+1
Update vc3_get_div() to avoid divide by zero operation on vc3_div_round_rate() by returning1, if there is no table match found. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-2-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: stm32mp1: use stm32mp13 reset driverGabriel Fernandez7-128/+42
STM32MP15 is now using the same reset driver as STM32MP13 as they have the same binding requirement. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20231208143700.354785-3-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: stm32mp1: move stm32mp1 clock driver into stm32 directoryGabriel Fernandez5-11/+31
Move all STM32MP clock drivers into same directory (stm32). Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20231208143700.354785-2-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: rs9: Add support for 9FGV0841Marek Vasut1-0/+9
This model is similar to 9FGV0441, the DIFx bits start at bit 0 again, except this chip has 8 outputs. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20231113221949.111964-4-marek.vasut+renesas@mailbox.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: rs9: Replace model check with bitshift from chip dataMarek Vasut1-17/+9
Adjust rs9_calc_dif() to special-case the 9FGV0241 where DIFx bits start at 1, encode this shift into chip data and drop the model check entirely. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20231113221949.111964-3-marek.vasut+renesas@mailbox.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: rs9: Limit check to vendor ID in VID registerMarek Vasut1-0/+2
Extract only vendor ID from VID register, the top 4 bits are revision ID which are not useful for the vendor ID check. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20231113221949.111964-2-marek.vasut+renesas@mailbox.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clocking-wizard: Add support for versal clocking wizardShubhrajyoti Datta1-92/+536
Add support for Clocking Wizard for Versal adaptive compute acceleration platforms. The Versal clocking wizard differs in the programming model and the register layout. The CLKFBOUT_1 registers are at offset of 0x200 instead of the 0x330 in Versal. In Versal clocking wizard the low and high time is programmed instead of the divisor. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://lore.kernel.org/r/20231214105125.26919-3-shubhrajyoti.datta@amd.com [sboyd@kernel.org: Stop initializing spinlock flags] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: microchip: mpfs-ccc: replace include of asm-generic/errno-base.hConor Dooley1-1/+1
As evidenced by the fact that only 2 other drivers include this header, it is not a normal thing to do. Including the regular version of this header is far more conventional for drivers. Acked-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231214-dipper-earshot-72eef3059961@spud Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-18clk: rs9: Fix DIF OEn bit placement on 9FGV0241Marek Vasut1-1/+1
On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment the index in BIT() macro instead of the result of BIT() macro to shift the bit correctly on 9FGV0241. Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit calculation") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20231105200642.62792-1-marek.vasut+renesas@mailbox.org Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17drivers: clk: zynqmp: update divider round rate logicJay Buddhabhatti1-61/+5
Currently zynqmp divider round rate is considering single parent and calculating rate and parent rate accordingly. But if divider clock flag is set to SET_RATE_PARENT then its not trying to traverse through all parent rate and not selecting best parent rate from that. So use common divider_round_rate() which is traversing through all clock parents and its rate and calculating proper parent rate. Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20231129112916.23125-3-jay.buddhabhatti@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17drivers: clk: zynqmp: calculate closest mux rateJay Buddhabhatti1-1/+1
Currently zynqmp clock driver is not calculating closest mux rate and because of that Linux is not setting proper frequency for CPU and not able to set given frequency for dynamic frequency scaling. E.g., In current logic initial acpu clock parent and frequency as below apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y acpu0 0 0 0 2199999978 0 0 50000 Y After changing acpu frequency to 549999994 Hz using CPU freq scaling its selecting incorrect parent which is not closest frequency. rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y acpu0_mux 0 0 0 1599999984 0 0 50000 Y acpu0_div1 0 0 0 533333328 0 0 50000 Y acpu0 0 0 0 533333328 0 0 50000 Y Parent should remain same since 549999994 = 2199999978 / 4. So use __clk_mux_determine_rate_closest() generic function to calculate closest rate for mux clock. After this change its selecting correct parent and correct clock rate. apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_div1 0 0 0 549999995 0 0 50000 Y acpu0 0 0 0 549999995 0 0 50000 Y Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20231129112916.23125-2-jay.buddhabhatti@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: mmp: pxa168: Fix memory leak in pxa168_clk_init()Kuan-Wei Chiu1-0/+3
In cases where mapping of mpmu/apmu/apbc registers fails, the code path does not handle the failure gracefully, potentially leading to a memory leak. This fix ensures proper cleanup by freeing the allocated memory for 'pxa_unit' before returning. Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Link: https://lore.kernel.org/r/20231210175232.3414584-1-visitorckw@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: hi3620: Fix memory leak in hi3620_mmc_clk_init()Kuan-Wei Chiu1-1/+3
In cases where kcalloc() fails for the 'clk_data->clks' allocation, the code path does not handle the failure gracefully, potentially leading to a memory leak. This fix ensures proper cleanup by freeing the allocated memory for 'clk_data' before returning. Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Link: https://lore.kernel.org/r/20231210165040.3407545-1-visitorckw@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: sp7021: fix return value check in sp7021_clk_probe()Yang Yingliang1-6/+6
devm_platform_ioremap_resource() never returns NULL pointer, it will return ERR_PTR() when it fails, so replace the check with IS_ERR(). Fixes: d54c1fd4a51e ("clk: Add Sunplus SP7021 clock driver") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20231128133016.2494699-1-yangyingliang@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-16clk: qcom: camcc-sc8280xp: Prevent error pointer dereferenceDan Carpenter1-2/+3
If "regmap" is an error pointer then calling regmap_update_bits() will crash. We only need to call regmap_update_bits() if we had written to it earlier. Fixes: ff93872a9c61 ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/210d48ce-6ebc-4a6b-b30f-866d10d41a16@moroto.mountain Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16clk: qcom: videocc-sm8150: Add runtime PM supportSatya Priya Kakitapalli1-2/+18
Add runtime PM support to ensure the supply rails are enabled when necessary. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-4-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16clk: qcom: videocc-sm8150: Add missing PLL config propertySatya Priya Kakitapalli1-0/+1
When the driver was ported upstream, PLL test_ctl_hi1 register value was omitted. Add it to ensure the PLLs are fully configured. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-3-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16clk: qcom: videocc-sm8150: Update the videocc resetsSatya Priya Kakitapalli1-0/+4
Add all the available resets for the video clock controller on sm8150. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-2-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-14Merge tag 'v6.7-rockchip-clkfixes1' of ↵Stephen Boyd2-15/+10
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Pull Rockchip clk driver fixes for the merge window from Heiko Stuebner: Fixes for a wrong clockname, a wrong clock-parent, a wrong clock-gate and finally one new PLL rate for the rk3568 to fix display artifacts on a handheld devices based on that soc. * tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name clk: rockchip: rk3128: Fix aclk_peri_src's parent clk: rockchip: rk3128: Fix HCLK_OTG gate register clk: rockchip: rk3568: Add PLL rate for 292.5MHz
2023-12-13clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1Claudiu Beznea1-0/+10
RZ/G3S has 2 Gigabit Ethernet interfaces available. Add clock and reset support for both of them. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13clk: renesas: rzg2l: Check reset monitor registersClaudiu Beznea1-15/+44
The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset monitor registers need to be interrogated when the reset signals are toggled (chapters "Procedures for Supplying and Stopping Reset Signals" and "Procedure for Activating Modules"). Without this, there is a chance that different modules (e.g. Ethernet) are not ready after their reset signal is toggled, leading to failures (on probe or resume from deep sleep states). The same indications are available for RZ/V2M for TYPE-B reset controls. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Fixes: 8090bea32484 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13clk: renesas: r9a08g045: Add IA55 pclk and its resetClaudiu Beznea1-0/+3
An IA55 interrupt controller is available on the RZ/G3S SoC. Add the IA55 pclk and its reset. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-12clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm supportPeter Griffin2-0/+2512
cmu_top is the top level clock management unit which contains PLLs, muxes, dividers and gates that feed the other clock management units. cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the APM module. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-9-peter.griffin@linaro.org [krzysztof: drop not needed linux/of_device.h include] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-12clk: samsung: clk-pll: Add support for pll_{0516,0517,518}Peter Griffin2-0/+9
These plls are found in the Tensor gs101 SoC found in the Pixel 6. pll0516x: Integer PLL with high frequency pll0517x: Integer PLL with middle frequency pll0518x: Integer PLL with low frequency PLL0516x FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) PLL0517x and PLL0518x FOUT = (MDIV * FIN)/PDIV*2^SDIV) The PLLs are similar enough to pll_0822x that the same code can handle both. The main difference is the change in the fout formula for the high frequency 0516 pll. Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor. MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x. When defining the PLL the "con" parameter should be set to CON3 register, like this PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-8-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-08clk: qcom: rpmh: Add support for X1E80100 rpmh clocksRajendra Nayak1-0/+24
Adds the RPMH clocks present in X1E80100 SoC Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-5-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08clk: qcom: Add Global Clock controller (GCC) driver for X1E80100Rajendra Nayak3-0/+6818
Add support for the global clock controller found on X1E80100 based devices. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-3-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000Imran Shaik3-0/+2466
Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: branch: Add mem ops support for branch2 clocksTaniya Das2-0/+59
Add the support for mem ops implementation to handle the sequence of enable/disable of the memories in ethernet PHY, prior to enable/disable of the respective clocks, which helps retain the respecive block's register contents. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: gpucc-sm8150: Update the gpu_cc_pll1 configSatya Priya Kakitapalli1-2/+2
Update the test_ctl_hi_val and test_ctl_hi1_val of gpu_cc_pll1 as per latest HW recommendation. Fixes: 0cef71f2ccc8 ("clk: qcom: Add graphics clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231122042814.4158076-1-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: rpmh: add clocks for SM8650Neil Armstrong1-0/+34
Add RPMH Clocks for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-11-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 GPU Clock Controller driverNeil Armstrong3-0/+670
Add Graphics Clock Controller (GPUCC) support for SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-10-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 Display Clock Controller driverNeil Armstrong3-0/+1821
Add Display Clock Controller (DISPCC) support for SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-9-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 TCSR Clock Controller driverNeil Armstrong3-0/+191
Add TCSR Clock Controller support for SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-8-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 Global Clock Controller driver, part 2Neil Armstrong3-0/+345
Add Global Clock Controller (GCC) driver plumbing for the SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-7-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 Global Clock Controller driver, part 1Neil Armstrong1-0/+3514
Add Global Clock Controller (GCC) tables for the SM8650 platform, the driver plumbing will be added afterwards. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-6-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: gcc-msm8939: Add missing CSI2 related clocksVincent Knecht1-3/+107
When adding in the indexes for this clock-controller we missed GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK, GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK. Add them in now and rename ftbl_gcc_camss_csi0_1_clk to account for csi2 also using it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20231029061948.505883-2-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCCBryan O'Donoghue3-0/+3054
Add the sc8280xp CAMCC driver which follows the sdm845 CAMCC lineage with additional CCI and IFE blocks and more granular clock parentage. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231026105345.3376-4-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-05clk: rockchip: rk3568: Mark pclk_usb as criticalChris Morgan1-0/+1
In the reference manual under "2.8.6 NIU Clock gating reliance" it is stated that pclk_usb_niu has a dependency on hclk_usb_niu. While the manual does not state that this is a bi-directional relationship it was noted that the sdmmc2 failed to operate for me in mmc mode if the pclk_usb was not marked as critical. The parent clock of the hclk_sdmmc2 is hclk_usb. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20231204185719.569021-8-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-05clk: rockchip: rk3568: Add PLL rate for 126.4MHzChris Morgan1-0/+1
Add support for a PLL rate of 126.4MHz so that the Powkiddy X55 panel can run at a requested 60hz. I have confirmed this rate fits with all the constraints listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter 2 Clock & Reset Unit (CRU)." Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20231204185719.569021-9-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-03clk: qcom: apss-ipq-pll: add support for IPQ5018Gokul Sriram Palanisamy1-0/+21
IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets, add configuration values and the compatible. Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230925102826.405446-3-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-11-28clk: rockchip: rk3128: Fix SCLK_SDMMC's clock nameAlex Bee1-1/+1
SCLK_SDMMC is the parent for SCLK_SDMMC_DRV and SCLK_SDMMC_SAMPLE, but used with the (more) correct name sclk_sdmmc. SD card tuning does currently fail as the parent can't be found under that name. There is no need to suffix the name with '0' since RK312x SoCs do have a single sdmmc controller - so rename it to the name which is already used by it's children. Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20231127181415.11735-6-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-11-28clk: rockchip: rk3128: Fix aclk_peri_src's parentFinley Xiao1-13/+7
According to the TRM there are no specific gpll_peri, cpll_peri, gpll_div2_peri or gpll_div3_peri gates, but a single clk_peri_src gate. Instead mux_clk_peri_src directly connects to the plls respectively the pll divider clocks. Fix this by creating a single gated composite. Also rename all occurrences of aclk_peri_src to clk_peri_src, since it is the parent for peri aclks, pclks and hclks. That name also matches the one used in the TRM. Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128") Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [renamed aclk_peri_src -> clk_peri_src and added commit message] Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20231127181415.11735-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-11-28clk: qcom: Fix SM_CAMCC_8550 dependenciesJagadeesh Kona1-0/+1
SM_GCC_8550 depends on ARM64 but it is selected by SM_CAMCC_8550, which should have the same dependencies as SM_GCC_8550 to avoid the below Kconfig warning reported by kernel test robot. WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_CAMCC_8550 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311062309.XugQH7AH-lkp@intel.com/ Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Link: https://lore.kernel.org/r/20231107064545.13120-1-quic_jkona@quicinc.com Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-11-27clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()Claudiu Beznea1-23/+15
Code in rzg2l_cpg_reset() is equivalent with the combined code of rzg2l_cpg_assert() and rzg2l_cpg_deassert(). There is no need to have different versions thus re-use rzg2l_cpg_assert() and rzg2l_cpg_deassert(). Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231120070024.4079344-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-20 06:22:40 +0300