summaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Collapse)AuthorFilesLines
2022-12-06clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_namesDmitry Baryshkov1-239/+253
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221204124508.1415713-6-dmitry.baryshkov@linaro.org
2022-12-06clk: qcom: gcc-msm8974: move clock parent tables downDmitry Baryshkov1-49/+49
Rearrage clock parent tables and PLL declarations (pull parents down and gpll4 up), so that we can use pll hw clock fields in the next commit. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221204124508.1415713-5-dmitry.baryshkov@linaro.org
2022-12-06clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov1-55/+55
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221204124508.1415713-4-dmitry.baryshkov@linaro.org
2022-12-06clk: qcom: gcc-ipq4019: switch to devm_clk_notifier_registerRobert Marko1-9/+2
Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221205113545.575702-1-robert.marko@sartura.hr
2022-12-02clk: qcom: rpmh: remove usage of platform nameDmitry Baryshkov1-171/+171
Now that all clocks have individual names, remove the names of SoCs from the RPMH clock definitions. Replace it with the common clk_rpmh_ prefix. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-9-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: rename VRM clock dataDmitry Baryshkov1-129/+129
RPMH VRM clocks are frequently shared between several platforms. It makes little sense to encode the SoC name into the clock name, if the same clock is used for other SoCs. Rework the VRM clock definitions to add resource-specific suffix. Keep the userspace-visible clock name, but encode the part of cmd resource and the divider into the variable name. This also make it obvious which variant is used, making the code less error-prone. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-8-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: rename ARC clock dataDmitry Baryshkov1-31/+31
RPMH ARC clocks are frequently shared between several platforms. It makes little sense to encode the SoC name into the clock name, if the same clock is used for other SoCs. Rework the ARC clock definitions to remove the SoC name. Keep the userspace-visible clock name, but encode the divider into the variable name. This also makes it obvious which divider is used by the platform, making the code less error-prone. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-7-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: support separate symbol name for the RPMH clocksDmitry Baryshkov1-8/+8
Both ARC and VRM clocks have minor differences between platforms. However using SoC names directly results in duplication, confusion and occasional errors. Next patches are going to drop the SoC names and encode these differences into the clock names. To keep the system clock names (visible to userspace) intact, add separate symbol names that are used in the code. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-6-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: remove platform names from BCM clocksDmitry Baryshkov1-26/+26
There are no platform-specific parts in the BCM clocks, drop the platform name from the clock definitions, replacing it with clk_rpmh to have the common prefix. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-5-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: drop all _ao namesDmitry Baryshkov1-32/+30
In preparation for the further cleanup, remove the active only names, they can be easily generated from the standard ones. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-4-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: reuse common duplicate clocksDmitry Baryshkov1-15/+9
After the grouping it is obvious that some of the clock definitions are pure duplicates. Rename them to use a single common name for the clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-3-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpmh: group clock definitions togetherDmitry Baryshkov1-29/+26
In preparations to the further changes, group all RPMH clock definitions to ease review. Group the clocks by their type to make similar/duplicate clocks stand out. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202185843.721673-2-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpm: drop the platform from clock definitionsDmitry Baryshkov1-105/+89
A single clock definition can be used on different platforms. Thus the platform part of the clock name is not correct (and can be misleading). Remove the platform-specific part of the defined clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202070814.482470-5-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpm: drop the _clk suffix completelyDmitry Baryshkov1-10/+10
Drop the _clk suffix from other clocks too. This does not produce any user-visible changes, just syntax sugar. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202070814.482470-4-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpm: drop separate active-only namesDmitry Baryshkov1-34/+34
To simplify code reviews remove duplication between normal and active-only clock names. Get a single clock name and generate both names internally. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202070814.482470-3-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: rpm: remove unused active-only clock namesDmitry Baryshkov1-9/+9
The RPM_FIXED and RPM_XO_BUFFER clocks do not have the active-only counterparts. Drop corresponding unused arguments. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202070814.482470-2-dmitry.baryshkov@linaro.org
2022-12-02clk: qcom: Add GCC driver for SM8550Abel Vesa3-0/+3396
Add Global Clock controller (GCC) driver for SM8550 SoC, which includes the gcc resets and gdsc. This patch is based on an initial downstream driver. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-6-abel.vesa@linaro.org
2022-12-02clk: qcom: Add LUCID_OLE PLL type for SM8550Abel Vesa2-0/+21
Add a LUCID_OLE PLL type for SM8550 SoC from Qualcomm. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-5-abel.vesa@linaro.org
2022-12-02clk: qcom: gdsc: Increase status poll timeoutAbel Vesa1-1/+2
The SM8550 GCC GDSCs need a higher timeout value when polling for status, so increase it to 1500us, while leaving the delay between disable-enable sequence for votable gdscs to stay the same. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-4-abel.vesa@linaro.org
2022-12-02clk: qcom: gcc-msm8939: Add rates to the GP clocksLin, Meng-Bo1-0/+35
Similar to msm8916, msm8939 has (at least) 6 "General Purpose" clocks that can be muxed to SoC pins. These clocks are: GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux) GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself) GP_MN : GPIO_110 (Doesn't seem to be described in gcc, ignored in this patch) Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. Reference: https://lore.kernel.org/r/20220612145955.385787-5-nikita@trvn.ru Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221117171343.24216-1-linmengbo0689@protonmail.com
2022-12-02clk: qcom: hfpll: use devm_platform_get_and_ioremap_resource()Minghao Chi1-3/+1
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/202211171403340042731@zte.com.cn
2022-12-02clk: qcom: ipq8074: populate fw_name for all parentsRobert Marko1-26/+26
It appears that having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for all parent clocks in parent_data. Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data") Co-developed-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
2022-12-02clk: qcom: krait-cc: convert to parent_data APIChristian Marangi1-90/+112
Modernize the krait-cc driver to parent-data API and refactor to drop any use of parent_names. From Documentation all the required clocks should be declared in DTS so fw_name can be correctly used to get the parents for all the muxes. .name is also declared to save compatibility with old DT. While at it also drop some hardcoded index and introduce an enum to make index values more clear. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com
2022-12-02clk: qcom: krait-cc: convert to devm_clk_hw_registerChristian Marangi1-12/+19
clk_register is now deprecated. Convert the driver to devm_clk_hw_register. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com
2022-12-02clk: qcom: krait-cc: handle secondary mux sourcing out of acpu_auxChristian Marangi1-4/+4
Some bootloader may leave the system in an even more undefined state with the secondary mux of L2 or other cores sourcing out of the acpu_aux parent. This results in the clk set to the PXO rate or a PLL8 rate. The current logic to reset the mux and set them to a defined state only handle if the mux are configured to source out of QSB. Change this and force a new and defined state if the current clk is lower than the aux rate. This way we can handle any wrong configuration where the mux is sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1), PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz). Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com
2022-12-02clk: qcom: krait-cc: also enable secondary mux and div clkChristian Marangi1-1/+20
clk-krait ignore any rate change if clk is not flagged as enabled. Correctly enable the secondary mux and div clk to correctly change rate instead of silently ignoring the request. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com
2022-12-02clk: qcom: krait-cc: fix wrong parent order for secondary muxChristian Marangi1-1/+1
The secondary mux parent order is swapped. This currently doesn't cause problems as the secondary mux is used for idle clk and as a safe clk source while reprogramming the hfpll. Each mux have 2 or more output but he always have a safe source to switch while reprogramming the connected pll. We use a clk notifier to switch to the correct parent before clk core can apply the correct rate. The parent to switch is hardcoded in the mux struct. For the secondary mux the safe source to use is the qsb parent as it's the only fixed clk as the acpus_aux is a pll that can source from pxo or from pll8. The hardcoded safe parent for the secondary mux is set to index 0 that in the secondary mux map is set to 2. But the index 0 is actually acpu_aux in the parent list. Fix the swapped parents to correctly handle idle frequency and output a sane clk_summary report. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com
2022-12-02clk: qcom: krait-cc: use devm variant for clk notifier registerChristian Marangi1-1/+1
Use devm variant for clk notifier register and correctly handle free resource on driver remove. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com
2022-12-02clk: qcom: clk-krait: fix wrong div2 functionsChristian Marangi1-0/+2
Currently div2 value is applied to the wrong bits. This is caused by a bug in the code where the shift is done only for lpl, for anything else the mask is not shifted to the correct bits. Fix this by correctly shift if lpl is not supported. Fixes: 4d7dc77babfe ("clk: qcom: Add support for Krait clocks") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221108215625.30186-1-ansuelsmth@gmail.com
2022-12-02clk: qcom: kpss-xcc: register it as clk providerChristian Marangi1-4/+9
krait-cc use this driver for the secondary mux. Register it as a clk provider to correctly use this clk in other drivers. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com
2022-12-02clk: qcom: ipq8074: add missing networking resetsRobert Marko1-0/+14
Downstream QCA 5.4 kernel defines networking resets which are not present in the mainline kernel but are required for the networking drivers. So, port the downstream resets and avoid using magic values for mask, construct mask for resets which require multiple bits to be set/cleared. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
2022-12-02clk: qcom: reset: support resetting multiple bitsRobert Marko2-2/+3
This patch adds the support for giving the complete bitmask in reset structure and reset operation will use this bitmask for all reset operations. Currently, reset structure only takes a single bit for each reset and then calculates the bitmask by using the BIT() macro. However, this is not sufficient anymore for newer SoC-s like IPQ8074, IPQ6018 and more, since their networking resets require multiple bits to be asserted in order to properly reset the HW block completely. So, in order to allow asserting multiple bits add "bitmask" field to qcom_reset_map, and then use that bitmask value if its populated in the driver, if its not populated, then we just default to existing behaviour and calculate the bitmask on the fly. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com
2022-12-02clk: qcom: lpass-sc7180: Avoid an extra "struct dev_pm_ops"Douglas Anderson1-7/+3
The two devices managed by lpasscorecc-sc7180.c each had their own "struct dev_pm_ops". This is not needed. They are exactly the same and the structure is "static const" so it can't possible change. combine the two. This matches what's done for sc7280. This should be a noop other than saving a few bytes. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104064055.3.I90ba14a47683a484f26531a08f7b46ace7f0a8a9@changeid
2022-12-02clk: qcom: lpass-sc7180: Fix pm_runtime usageDouglas Anderson1-8/+16
The sc7180 lpass clock controller's pm_runtime usage wasn't broken quite as spectacularly as the sc7280's pm_runtime usage, but it was still broken. Putting some printouts in at boot showed me this (with serial console enabled, which makes the prints slow and thus changes timing): [ 3.109951] DOUG: my_pm_clk_resume, usage=1 [ 3.114767] DOUG: my_pm_clk_resume, usage=1 [ 3.664443] DOUG: my_pm_clk_suspend, usage=0 [ 3.897566] DOUG: my_pm_clk_suspend, usage=0 [ 3.910137] DOUG: my_pm_clk_resume, usage=1 [ 3.923217] DOUG: my_pm_clk_resume, usage=0 [ 4.440116] DOUG: my_pm_clk_suspend, usage=-1 [ 4.444982] DOUG: my_pm_clk_suspend, usage=0 [ 14.170501] DOUG: my_pm_clk_resume, usage=1 [ 14.176245] DOUG: my_pm_clk_resume, usage=0 ...or this w/out serial console: [ 0.556139] DOUG: my_pm_clk_resume, usage=1 [ 0.556279] DOUG: my_pm_clk_resume, usage=1 [ 1.058422] DOUG: my_pm_clk_suspend, usage=-1 [ 1.058464] DOUG: my_pm_clk_suspend, usage=0 [ 1.186250] DOUG: my_pm_clk_resume, usage=1 [ 1.186292] DOUG: my_pm_clk_resume, usage=0 [ 1.731536] DOUG: my_pm_clk_suspend, usage=-1 [ 1.731557] DOUG: my_pm_clk_suspend, usage=0 [ 10.288910] DOUG: my_pm_clk_resume, usage=1 [ 10.289496] DOUG: my_pm_clk_resume, usage=0 It seems to be doing roughly the right sequence of calls, but just like with sc7280 this is more by luck than anything. Having a usage of -1 is just not OK. Let's fix this like we did with sc7280. Signed-off-by: Douglas Anderson <dianders@chromium.org> Fixes: ce8c195e652f ("clk: qcom: lpasscc: Introduce pm autosuspend for SC7180") Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104064055.2.I49b25b9bda9430fc7ea21e5a708ca5a0aced2798@changeid
2022-12-02clk: qcom: lpass-sc7280: Fix pm_runtime usageDouglas Anderson1-34/+21
The pm_runtime usage in lpass-sc7280 was broken in quite a few ways. Specifically: 1. At the end of probe it called "put" twice. This is a no-no and will end us up with a negative usage count. Even worse than calling "put" twice, it never called "get" once. Thus after bootup it could be seen that the runtime usage of the devices managed by this driver was -2. 2. In some error cases it manually called pm_runtime_disable() even though it had previously used devm_add_action_or_reset() to set this up to be called automatically. This meant that in these error cases we'd double-call pm_runtime_disable(). 3. It forgot to call undo pm_runtime_use_autosuspend(), which can sometimes have subtle problems (and the docs specifically mention that you need to undo this function). Overall the above seriously calls into question how this driver is working. It seems like a combination of "it doesn't", "by luck", and "because of the weirdness of runtime_pm". Specifically I put a printout to the serial console every time the runtime suspend/resume was called for the two devices created by this driver (I wrapped the pm_clk calls). When I had serial console enabled, I found that the calls got resumed at bootup (when the clk core probed and before our double-put) and then never touched again. That's no good. [ 0.829997] DOUG: my_pm_clk_resume, usage=1 [ 0.835487] DOUG: my_pm_clk_resume, usage=1 When I disabled serial console (speeding up boot), I got a different pattern, which I guess (?) is better: [ 0.089767] DOUG: my_pm_clk_resume, usage=1 [ 0.090507] DOUG: my_pm_clk_resume, usage=1 [ 0.151885] DOUG: my_pm_clk_suspend, usage=-2 [ 0.151914] DOUG: my_pm_clk_suspend, usage=-2 [ 1.825747] DOUG: my_pm_clk_resume, usage=-1 [ 1.825774] DOUG: my_pm_clk_resume, usage=-1 [ 1.888269] DOUG: my_pm_clk_suspend, usage=-2 [ 1.888282] DOUG: my_pm_clk_suspend, usage=-2 These different patterns have to do with the fact that the core PM Runtime code really isn't designed to be robust to negative usage counts and sometimes may happen to stumble upon a behavior that happens to "work". For instance, you can see that __pm_runtime_suspend() will treat any non-zero value (including negative numbers) as if the device is in use. In any case, let's fix the driver to be correct. We'll hold a pm_runtime reference for the whole probe and then drop it (once!) at the end. We'll get rid of manual pm_runtime_disable() calls in the error handling. We'll also switch to devm_pm_runtime_enable(), which magically handles undoing pm_runtime_use_autosuspend() as of commit b4060db9251f ("PM: runtime: Have devm_pm_runtime_enable() handle pm_runtime_dont_use_autosuspend()"). While we're at this, let's also use devm_pm_clk_create() instead of rolling it ourselves. Note that the above changes make it obvious that lpassaudio_create_pm_clks() was doing more than just creating clocks. It was also setting up pm_runtime parameters. Let's rename it. All of these problems were found by code inspection. I started looking at this driver because it was involved in a deadlock that I reported a while ago [1]. Though I bisected the deadlock to commit 1b771839de05 ("clk: qcom: gdsc: enable optional power domain support"), it was never really clear why that patch affected it other than a luck of timing changes. I'll also note that by fixing the timing (as done in this change) we also seem to aboid the deadlock, which is a nice benefit. Also note that some of the fixes here are much the same type of stuff that Dmitry did in commit 72cfc73f4663 ("clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create"), but I guess lpassaudiocc-sc7280.c didn't exist then. [1] https://lore.kernel.org/r/20220922154354.2486595-1-dianders@chromium.org Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104064055.1.I00a0e4564a25489e85328ec41636497775627564@changeid
2022-11-29clk: visconti: Fix memory leak in visconti_register_pll()Xiu Jianfeng1-0/+1
@pll->rate_table has allocated memory by kmemdup(), if clk_hw_register() fails, it should be freed, otherwise it will cause memory leak issue, this patch fixes it. Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com> Link: https://lore.kernel.org/r/20221122152353.204132-1-xiujianfeng@huawei.com Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-11-29clk: mediatek: fix dependency of MT7986 ADC clocksDaniel Golle1-1/+1
It seems like CLK_INFRA_ADC_FRC_CK always need to be enabled for CLK_INFRA_ADC_26M_CK to work. Instead of adding this dependency to the mtk-thermal and mt6577_auxadc drivers, add dependency to the clock driver clk-mt7986-infracfg.c. Fixes: ec97d23c8e22 ("clk: mediatek: add mt7986 clock support") Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/5e55012567da74870e1fb2edc2dc513b5821e523.1666801017.git.daniel@makrotopia.org Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: Change PLL register API for MT8186Johnson Wang2-3/+64
Use mtk_clk_register_pllfhs() to enhance frequency hopping and spread spectrum clocking control for MT8186. Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221121122957.21611-5-johnson.wang@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: Add new clock driver to handle FHCTL hardwareJohnson Wang6-0/+635
To implement frequency hopping and spread spectrum clocking function, we introduce new clock type and APIs to handle FHCTL hardware. Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221121122957.21611-4-johnson.wang@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: Export PLL operations symbolsJohnson Wang2-50/+89
Export PLL operations and register functions for different type of clock driver used. Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221121122957.21611-2-johnson.wang@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt8186-topckgen: Add GPU clock mux notifierAngeloGioacchino Del Regno1-0/+27
Following the changes done to MT8183, MT8192, MT8195, register a clock notifier for MT8186, allowing safe clockrate updates for the MFG PLL. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-11-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt8186-mfg: Propagate rate changes to parentAngeloGioacchino Del Regno1-2/+3
Propagate the rate changes to MFG_BG3D's parent on MT8186 to allow for proper GPU DVFS. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-10-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt8195-topckgen: Drop flags for main/univpll fixed factorsAngeloGioacchino Del Regno1-39/+39
The main/univpll clocks are used as clock sources for multiple peripherals of different kind, some of which are critical (like AXIs); a rate change on any of these two will produce a rate change on many devices and that's likely to produce system instability if not done correctly: this is the reason why we have (a lot of) "fixed factor" main/univpll divider clocks, used by MUX clocks to provide different rates based on PLL output dividers. Following what was done on clk-mt8186-topckgen and also preventing the same GPU DVFS issue, drop CLK_SET_RATE_PARENT from the aforementioned clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-9-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt8192: Drop flags for main/univpll fixed factorsAngeloGioacchino Del Regno1-38/+38
The main/univpll clocks are used as clock sources for multiple peripherals of different kind, some of which are critical (like AXIs); a rate change on any of these two will produce a rate change on many devices and that's likely to produce system instability if not done correctly: this is the reason why we have (a lot of) "fixed factor" main/univpll divider clocks, used by MUX clocks to provide different rates based on PLL output dividers. Following what was done on clk-mt8186-topckgen and also preventing the same GPU DVFS issue, drop CLK_SET_RATE_PARENT from the aforementioned clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-8-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt6795-topckgen: Drop flags for main/sys/univpll fixed factorsAngeloGioacchino Del Regno1-38/+38
The main/sys/univpll clocks are used as clock sources for multiple peripherals of different kind, some of which are critical (like AXIs); a rate change on any of these two will produce a rate change on many devices and that's likely to produce system instability if not done correctly: this is the reason why we have (a lot of) "fixed factor" main/sys/univpll divider clocks, used by MUX clocks to provide different rates based on PLL output dividers. Following what was done on clk-mt8186-topckgen and also preventing the same GPU DVFS issue, drop CLK_SET_RATE_PARENT from the aforementioned clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-7-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factorsAngeloGioacchino Del Regno1-38/+38
The main/sys/univpll clocks are used as clock sources for multiple peripherals of different kind, some of which are critical (like AXIs); a rate change on any of these two will produce a rate change on many devices and that's likely to produce system instability if not done correctly: this is the reason why we have (a lot of) "fixed factor" main/sys/univpll divider clocks, used by MUX clocks to provide different rates based on PLL output dividers. Following what was done on clk-mt8186-topckgen and also preventing the same GPU DVFS issue, drop CLK_SET_RATE_PARENT from the aforementioned clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-6-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt8183: Drop flags for sys/univpll fixed factorsAngeloGioacchino Del Regno1-38/+38
The syspll and univpll clocks are used as clock sources for multiple peripherals of different kind, some of which are critical (like AXIs); a rate change on any of these two will produce a rate change on many devices and that's likely to produce system instability if not done correctly: this is the reason why we have (a lot of) "fixed factor" sys/univpll divider clocks, used by MUX clocks to provide different rates based on PLL output dividers. Following what was done on clk-mt8186-topckgen and also solving the same GPU DVFS issue, drop CLK_SET_RATE_PARENT from the aforementioned clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-5-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt8183: Compress top_divs array entriesAngeloGioacchino Del Regno1-144/+72
There's no need to split each FACTOR entry in two lines, as each of them does fit in one line just fine. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-4-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: mt8186-topckgen: Drop flags for main/univpll fixed factorsAngeloGioacchino Del Regno1-31/+31
The mainpll and univpll clocks are used as clock sources for multiple peripherals of different kind, some of which are critical (like AXIs); a rate change on any of these two will produce a rate change on many devices and that's likely to produce system instability if not done correctly: this is the reason why we have "fixed factor" clocks, used by MUX clocks to provide different rates based on PLL output dividers. Though, there's one fundamental issue that must be resolved somehow: When performing GPU DVFS, we get a rate request that will try to change the frequency of MAINPLL due to the CLK_TOP_MFG mux having clk26m, mfgpll (the GPU dedicated PLL), mainpll_d3, mainpll_d5 (fixed factor dividers) as possible parents. In order to solve that, there are two ways: 1. Add new "fake" mainpll_d3_fixed, mainpll_d5_fixed clocks, clones of mainpll_d3, mainpll_d5 clocks, for the only purpose of not declaring CLK_SET_RATE_PARENT; or 2. Simply drop said flag from the original dividers. After some careful validation, I cannot see anything calling a rate change request during runtime for MAINPLL, nor for UNIVPLL (which would, again, mean that we're reclocking lots of peripherals at once!), so it is safe *and sane* to simply remove the CLK_SET_RATE_PARENT flag to all of the main/univpll fixed factor divider clocks. Besides, if for any (doubtful) reason main/univpll rate change will be required in the future, it's still possible to call that on the PLL main clocks, so we're still covered anyway. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-3-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-11-29clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocksAngeloGioacchino Del Regno2-2/+7
Before this change, every mtk_fixed_factor clock forced clock flags to CLK_SET_RATE_PARENT: while this is harmless in some cases, it may not be desired in some others, especially when performing clock muxing on a clock having multiple parents of which one is a dedicated PLL and the others are not. This is especially seen on the GPU clocks on some SoCs, where we are muxing between multiple parents: a fixed clock (crystal), a programmable GPU PLL and one or more dividers for the MAINPLL, used for a number of devices; it happens that when a rate change is called for the GPU, the clock framework will try to satisfy the rate request by using one of the MAINPLL dividers, which have CLK_SET_RATE_PARENT and will set the rate on MAINPLL itself - overclocking or underclocking many devices in the system - and making it to lock up. Logically, it should be harmless (and would only reduce possible bugs) to change all of the univpll and mainpll related fixed factor clocks to not declare the CLK_SET_RATE_PARENT by default but, on some SoCs, this is also used for dividers of other PLLs for which a rate change based on the divider may be desired, hence introduce a new FACTOR_FLAGS() macro to use custom flags (or none) on selected fixed factor clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20221024102307.33722-2-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 07:21:57 +0300