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path: root/drivers/clk
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2017-01-21clk: imx7d: Add the OCOTP clockFabio Estevam1-0/+1
Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-21clk: bcm2835: Add leaf clock measurement support, disabled by defaultEric Anholt1-25/+119
This proved incredibly useful during debugging of the DSI driver, to see if our clocks were running at rate we requested. Let's leave it here for the next person interacting with clocks on the platform (and so that hopefully we can just hook it up to debugfs some day). Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-21clk: bcm2835: Register the DSI0/DSI1 pixel clocks.Eric Anholt1-12/+109
The DSI pixel clocks are muxed from clocks generated in the analog phy by the DSI driver. In order to set them as parents, we need to do the same name lookup dance on them as we do for our root oscillator. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-21clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.Eric Anholt1-14/+28
Our core PLLs are intended to be configured once and left alone. With the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would change PLLD just to get closer to the requested DSI clock, thus changing PLLD_PER, the UART and ethernet PHY clock rates downstream of it, and breaking ethernet. We *do* want PLLH to change so that PLLH_AUX can be exactly the value we want, though. Thus, we need to have a per-divider policy of whether to pass rate changes up. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-21clk: cs2000: add Suspend/Resume featureKhiem Nguyen1-0/+22
CS2000 needs re-setup when redume, otherwise, it can't handle correct clock rate. Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> [Kuninori: cleanup original patch] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-21clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut3-0/+802
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL. The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL. The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-21Merge tag 'v4.11-rockchip-clk1' of ↵Stephen Boyd8-13/+1067
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: A new clock-type for the 1-2 muxes per soc that are for whatever reason controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. * tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clk: add rockchip,grf property for RK3399 clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: use rk3288 isp_in clock ids clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: add rk3288 isp_in clock ids clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER clk: rockchip: add clock controller for rk3328 dt-bindings: add bindings for rk3328 clock controller clk: rockchip: add dt-binding header for rk3328 clk: rockchip: add new pll-type for rk3328 clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 clk: rockchip: add a clock-type for muxes based in the grf
2017-01-21Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd5-1041/+18
clk-next Pull Samsung clk updates from Sylwester Nawrocki: - addition of the CPU clock configuration data for Exynos4412 Prime SoC variant, - removal of driver for deprecated Exynos4415 SoC, - switching from the syscore to regular system sleep PM ops in the audio subsystem clocks controller driver, - updates of the definitions of some "Network On Chip" related clocks. * tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Remove Exynos4415 driver (SoC not supported anymore) clk: samsung: exynos-audss: Replace syscore PM with platform device PM clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
2017-01-21clk: imx6: don't restrict LDB mux changes on QuadPlusLucas Stach1-8/+13
The LDB mux/gate layout has been fixed on QuadPlus, so there is no need to restrict the LDB mux changes on this hardware, as the erratum preventing this from working properly is gone. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-21Merge tag 'clk-renesas-for-v4.11-tag1' of ↵Stephen Boyd1-0/+9
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk updates from Geert Uytterhoeven: - Add CAN and MSIOF related clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add MSIOF controller clocks clk: renesas: r8a7796: Add CAN FD peripheral clock clk: renesas: r8a7796: Add CANFD clock clk: renesas: r8a7796: Add CAN peripheral clock
2017-01-20clk: sunxi-ng: add support for V3s CCUIcenowy Zheng4-0/+666
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-18clk: meson-gxbb: Export HDMI clocksNeil Armstrong1-2/+2
Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18clk: rockchip: fix the incorrect pclk_edp div width for RK3399Xing Zheng1-1/+1
The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Tested-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-17clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-digMylène Josserand1-1/+1
The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-17Merge tag 'samsung-dt-4.11' of ↵Olof Johansson1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt Samsung DeviceTree update for v4.11: 1. Fixes for initial audio clocks configuration. 2. Enable sound on Odroid-X board. 3. Enable DMA for UART modules on Exynos5 SoCs. 4. Add CPU OPPs for Exynos4412 Prime (newer version of Exynos4412). This pulls necessary change in the clocks. 5. Remove Exynos4212. We do not have any mainline boards with it. This will simplify few bits later. * tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: remove Exynos4212 support (dead code) ARM: dts: exynos: Add CPU OPPs for Exynos4412 Prime clk: samsung: Add CPU clk configuration data for Exynos4412 Prime ARM: dts: exynos: Enable DMA support for UART modules on Exynos5 SoCs ARM: dts: exynos: Cleanup Odroid-X2 and enable sound on Odroid-X ARM: dts: exynos: Fix initial audio clocks configuration on Exynos4 boards ARM: dts: exynos: Correct clocks for Exynos4 I2S module Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-16clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)Krzysztof Kozlowski2-1023/+0
Support for Exynos4415 is going away because there are no internal nor external users. Since commit 46dcf0ff0de3 ("ARM: dts: exynos: Remove exynos4415.dtsi"), the platform cannot be instantiated so remove also the drivers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Kukjin Kim <kgene@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-13clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner1-2/+2
Add the newly added clock ids to the clock entries of the rk3066/rk3188 clock driver. We won't be needing them in the kernel for a bit yet but as they're used in the new u-boot ddr setup code/dts we should make sure the clock ids stay identical and do not differ. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: rockchip: use rk3288 isp_in clock idsJacob Chen1-1/+1
Reference the newly added isp clock-ids in the clock-tree. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: stm32f4: avoid uninitialized variable accessArnd Bergmann1-5/+7
The failure path in the newly added function tries to free an uninitialized pointer: drivers/clk/clk-stm32f4.c: In function 'stm32f4_rcc_init': drivers/clk/clk-stm32f4.c:1106:4: error: 'gate' may be used uninitialized in this function [-Werror=maybe-uninitialized] I'm adding an initialization to NULL here to make the kfree() succeed, and I'm also rearranging the cleanup so that the same kfree() is used for any error path, making the function slightly more robust against newly introduced bugs in the error handling. Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10Merge branch 'clk-fixes' into clk-nextStephen Boyd1-7/+7
* clk-fixes: clk/samsung: exynos542x: mark some clocks as critical
2017-01-10clk: cdce925: add support for CDCE913, CDCE937, and CDCE949Akinobu Mita2-30/+89
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator family. There are also CDCE913, CDCE937, CDCE949 which have different number of PLLs and outputs. The clk-cdce925 driver supports only CDCE925 in the family. This adds support for the CDCE913, CDCE937, CDCE949, too. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Michael Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: mdm9615: Add EBI2 clockZoran Markovic1-0/+30
Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: uniphier: remove unneeded #include <linux/delay.h>Masahiro Yamada1-1/+0
This include was needed to suppress build error when this driver was initially merged because <linux/regmap.h> did not include <linux/delay.h> at that time. (developers' headache across sub-systems) The root cause has been fixed by commit adf08d481b52 ("regmap: include <linux/delay.h> from include/linux/regmap.h"), so this line can be dropped now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: mvebu: adjust AP806 CPU clock frequencies to production chipThomas Petazzoni1-5/+23
This commit adjusts the list of possible "Sample At Reset" values that define the CPU clock frequency of the AP806 (part of Marvell Armada 7K/8K) to the values that have been validated with the production chip. Earlier values were preliminary. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10Merge branch 'clk-hi3660' into clk-nextStephen Boyd3-0/+575
* clk-hi3660: clk: hisilicon: Add clock driver for hi3660 SoC dt-bindings: Document the hi3660 clock bindings
2017-01-10clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao3-0/+575
Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Simplify probe with function pointer] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk/samsung: exynos542x: mark some clocks as criticalMarek Szyprowski1-7/+7
Some parent clocks of the Exynos542x clock blocks, which have separate power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always enabled to access any register related to power management unit or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused or even no flags) to prevent disabling them. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: clk-conf: Do not print error messages if EPROBE_DEFERGeert Uytterhoeven1-6/+9
EPROBE_DEFER is not an error, hence printing an error message like clk: couldn't get clock 0 for /soc/display@feb00000 may confuse the user. Suppress error messages in case of probe deferral to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: scpi: don't add cpufreq device if the scpi dvfs node is disabledSudeep Holla1-6/+8
Currently we add the virtual cpufreq device unconditionally even when the SCPI DVFS clock provider node is disabled. This will cause cpufreq driver to throw errors when it gets initailised on boot/modprobe and also when the CPUs are hot-plugged back in. This patch fixes the issue by adding the virtual cpufreq device only if the SCPI DVFS clock provider is available and registered. Fixes: 9490f01e2471 ("clk: scpi: add support for cpufreq virtual device") Reported-by: Michał Zegan <webczat_200@poczta.onet.pl> Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: qcom: Add GCC_MSS_RESET supportAvaneesh Kumar Dwivedi1-0/+1
Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: zte: add audio clocks for zx296718Jun Nie3-0/+275
The audio related clock support is missing from the existing zx296718 clock driver. Let's add it, so that the upstream ZX SPDIF driver can work for HDMI audio support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [sboyd@codeaurora.org: Staticize some more structures] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: zx296718: do not panic on failureShawn Guo1-9/+18
Instead of using panic, we should give an error message and return error code when of_clk_add_hw_provider() call fails. Since we have error prompt for failures, the "init over" pr_info output isn't really necessary but becomes a debug noise. So let's clean it up along the way. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: wm831x: fix usleep_range with bad rangeNicholas Mc Guire1-1/+2
The delay here is not in atomic context and does not seem critical with respect to precision, but usleep_range(min,max) with min==max results in giving the timer subsystem no room to optimize uncritical delays. Fix this by setting the range to 2000,3000 us. Fixes: commit f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver") Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2Nikita Yushchenko3-2/+102
On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by: Andrey Smirnov <andrew.smirnov@gmail.com> CC: Chris Healy <cphealy@gmail.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk/axs10x: Clear init field in driver probeJose Abreu1-0/+1
Init field must be cleared in driver probe as this structure is not dinamically allocated. If not, wrong flags can be passed to core. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: Carlos Palminha <palminha@synopsys.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Fixes: 923587aafc2c ("clk/axs10x: Add I2S PLL clock driver") Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com
2017-01-10Merge branches 'clk-qcom-rpm8974', 'clk-stm32f4', 'clk-ipq4019' and ↵Stephen Boyd4-40/+1136
'clk-fixes' into clk-next * clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
2017-01-07Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2-7/+24
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "One fix for a broken driver on Renesas RZ/A1 SoCs with bootloaders that don't turn all the clks on and another fix for stm32f4 SoCs where we have multiple drivers attaching to the same DT node" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
2017-01-06clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFERDouglas Anderson1-1/+0
When we used to defer setting the "grf" member to rockchip_clk_get_grf() it was important to init the "grf" member to an error value in rockchip_clk_init(). With recent changes, we now set "grf" right in rockchip_clk_init() (two lines below the place where we initted it). That makes the old init useless. Get rid of it. Fixes: 6f339dc2719e ("clk: rockchip: lookup General Register Files in rockchip_clk_init") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-05clk: rockchip: add clock controller for rk3328Elaine Zhang3-0/+914
Add the clock tree definition for the new rk3328 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-03clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper1-2/+2
As the SPDIF was rarely documented on the earlier Allwinner SoCs it was assumed that it had a similar clock register to the one described in the H3 User Manual. However this is not the case and it looks to shares the same setup as the I2S clock registers. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-03clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33Icenowy Zheng1-1/+1
The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-03clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng1-0/+10
When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high, and the system hangs. Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-03clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman1-0/+10
When adjusting PLL_CPUX on H3, the PLL is temporarily driven too high, and the system becomes unstable (oopses or hangs). Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Ondrej Jirman <megous@megous.com> Tested-by: Lutz Sammer <johns98@gmx.net> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-02clk: rockchip: add new pll-type for rk3328Elaine Zhang2-3/+14
The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask, the rk3328 soc pll mode only one bit(rk3036 soc have two bits) so these should be independent and separate from the series of rk3328s. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288Heiko Stuebner1-6/+5
With the newly introduced clk type for muxes in the grf we now can describe some missing clocks, like the aclk_vcodec that selects between aclk_vdpu and aclk_vepu based on a bit set in the general register files. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02clk: rockchip: add a clock-type for muxes based in the grfHeiko Stuebner4-0/+131
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the general register files. Add a clock-type that can control these as well, so that we don't need to work around them being absent. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-12-29clk: samsung: exynos-audss: Replace syscore PM with platform device PMMarek Szyprowski1-14/+10
Exynos AUDSS clock driver has been already converted to platform driver, so remove the dependency on the syscore ops - the last remaining non-platform driver feature. Platform device's system sleep PM provides all needed infrastructure for replacing syscore-based PM, so do it now. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-29clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as criticalChanwoo Choi1-4/+4
The ACLK_BUS0/1/2 are used for NoC (Network on Chip). If NoC's clocks are disabled, the system halt happens. Following clocks must be always enabled: - CLK_ACLK_BUS0_400 : NoC's bus clock for PERIC/PERIS/FSYS/MSCL, - CLK_ACLK_BUS1_400 : NoC's bus clock for MFC/HEVC/G3D, - CLK_ACLK_BUS2_400 : NoC's bus clock for GSCL/DISP/G2D/CAM0/CAM1/ISP. This patch also adds the CLK_SET_RATE_PARENT flag to the CLK_SCLK_JPEG_MSCL because this clock should be used for bus frequency scaling. This clock need to be changed on the fly with CLK_SET_RATE_PARENT flag. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-29clk: samsung: Add CPU clk configuration data for Exynos4412 PrimeBartlomiej Zolnierkiewicz1-0/+4
Add cpu clock configuration data for Exynos4412 Prime SoC (it supports additional PLL rates & CPU frequencies). Based on Hardkernel's kernel for ODROID-X2/U2/U3 boards. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-28clk: qcom: ipq4019: Add the cpu clock frequency change notifierAbhishek Sahu1-1/+39
The current driver code gives the crash or gets hang while switching the CPU frequency some time. The APSS CPU Clock divider is not glitch free so it the APPS clock need to be switched for stable clock during the change. This patch adds the frequency change notifier for APSS CPU clock. It changes the parent of this clock to stable PLL FEPLL500 for PRE_RATE_CHANGE event. This event will be generated before actual clock set operations. The clock set operation will again change its corresponding parent by getting the same from frequency table. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> [sboyd@codeaurora.org: Indent less in probe] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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