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path: root/drivers/clk
AgeCommit message (Collapse)AuthorFilesLines
2023-06-07driver/include/sound: Normalize the copyright licensesXingyu Wu9-9/+18
Normalize the copyright licenses about clocktree/watchdog/timer/spdif/pwmdac. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-01-13clk: starfive: Fixed UART3-5 error after resumeXingyu Wu1-5/+6
Fixed UART3-5 error after hibernation by adjusting register shift. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-01-11clk: starfive: Add funtions of saving and restoring data about SYS, AON and STGXingyu Wu2-0/+185
Add 'save_context' ops to save register value of clock and 'restore_context' ops to restore the value to register. The ops only suitable for SYS, AON and STG clock tree not ISP and VOUT. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-12-15clk: starfive: pll: Remove high frequency of PLL0Xingyu Wu1-23/+3
Remove high frequency of PLL0 and make sure PLL0 max frequency is 1.5GHz. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-12-15clk: starfive: Change divider value of cpu_core clockXingyu Wu1-1/+1
Change divider value to make sure the frequency is half of PLL0. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-11-14clk:starfive:vout:Add parent about disp_apb clkXingyu Wu1-2/+2
Clock "u0_pclk_mux_func_pclk" is the parent of "disp_apb" clock. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-11-14clk:starfive:vout:Add runtime and system pmXingyu Wu2-38/+111
Add runtime and system pm in vout clock tree driver. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-11-01clk: starfive: Keep the clock apb0 enabled alwaysHal Feng1-1/+1
This solves crush problem of i2c runtime pm and prevents some aon modules from working abnormally. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-10-28Merge branch 'CR_2412_515_Clocktree_PLL1_Xingyu.Wu' into 'jh7110-5.15.y-devel'andy.hu2-7/+1
CR_2412_515_Clocktree_PLL1_Xingyu.Wu See merge request sdk/linux!553
2022-10-28Merge branch 'CR_2440_515_Clocktree_1.5G_Xingyu.Wu' into 'jh7110-5.15.y-devel'andy.hu2-0/+36
CR_2440_515_Clocktree_1.5G_Xingyu.Wu See merge request sdk/linux!564
2022-10-27clk:starfive:isp:Add runtime and system pm controlXingyu Wu3-43/+126
Add runtime and system pm in isp clock tree driver. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-10-26clk:starfive:Count PLL1 rateXingyu Wu2-7/+1
Count PLL1 rate through reading syscon registers. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-10-26clk:starfive:Change PLL0 rate to 1.5GHzXingyu Wu2-0/+36
Change PLL0 rate to 1.5GHz and change cpu_core divider. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-09-06clk:starfive:Set pll2 default rate to 1188mXingyu Wu1-1/+1
Change pll2_out default rate from 1228.8m to 1188m. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-08-19clk:starfive:Modify 'stg_apb' clockXingyu Wu1-6/+5
Change 'stg_apb' clock from external clock to internal clock. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Update clk and reset api about voutxingyu.wu1-37/+22
Use 'clk_bulk_get' api to replace 'clk_get' and use 'share' replace 'exclusive' about reset. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Update clk and reset api about ispxingyu.wu1-105/+31
Use 'clk_bulk_get' and 'devm_reset_control_array_get' api to replace 'clk_get' and 'devm_reset_control_get' api. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Modify function format about 'jh7110_pll_data_from'xingyu.wu1-2/+2
Modify function format about 'jh7110_pll_data_from' Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Set PLL2 frequency when clock tree registeringxingyu.wu2-1/+14
In the file drivers/clk/starfive/clk-starfive-jh7110-pll.h, If set PLL2_DEFAULT_FREQ NULL of 0 , then PLL2 frequency is original. If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2 frequency will be set the new rate during clock tree registering. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Add PLL2 frequency controllerxingyu.wu4-25/+35
If enable CONFIG_CLK_STARFIVE_JH7110_PLL, also could read or set PLL1 clock's rate by reading or setting syscon registers. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Add PLL0 frequency controllerxingyu.wu7-2/+765
If enable CONFIG_CLK_STARFIVE_JH7110_PLL, could read or set PLL0 clock's rate by reading or setting syscon registers. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Modify the formatxingyu.wu7-110/+119
Modify the clocktree files' format Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20dt-bindings:clock:Delete external clock definitionsxingyu.wu5-0/+40
Move external clock definitions to C files that avoid illegal use. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-01clk:starfive:Update pmu Apixingyu.wu2-4/+14
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-06-08clk:starfive:jh7110: Change uart3-uart5 clk register infoyanhong.wang2-3/+13
The core_clk division register of uart3-uart5 include fractional and integral parts,but now only use the integral part,so include shift operation. The integral part include 8 bit,so the max value can be configed is 255.In order to support 115200 bandrate,so limit the max value to 10. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-05-30clk:starfive:Adjust clocks' flagxingyu.wu1-18/+18
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-05-25Merge branch 'CR_1051_CLOCK_TREE_Xingyu.Wu' into 'jh7110-5.15.y-devel'andy.hu2-36/+40
Cr 1051 clock tree xingyu.wu See merge request sdk/linux!83
2022-05-24clk:starfive:Modify the definitions instead of numbers in vout clock treexingyu.wu1-14/+18
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-05-24clk:starfive:Modify the critical clocks' flagsxingyu.wu1-22/+22
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-05-23Merge branch 'CR_1035_CLOCK_TREE_VOUT_Xingyu.Wu' into 'jh7110-5.15.y-devel'andy.hu1-1/+65
clk:starfive:Add top clocks and reset in vout clock tree See merge request sdk/linux!78
2022-05-23clk:starfive:jh7110: pll0 switches to 1250M.samin1-1/+1
pll0 switches to 1250M by spl. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-05-20clk:starfive:Add top clocks and reset in vout clock treexingyu.wu1-1/+65
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-05-17clk:starfive:Change some clocks to 'ignore-unused'xingyu.wu4-17/+17
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-05-15clk:starfive:Change PLL0 dafalut value from 1250m to 1000mxingyu.wu1-1/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-05-15driver:clk:Add noc clock initialization in isp clock tree driverxingyu.wu1-8/+72
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-05-15clk:starfive:Modify the clock to 'CLK_IGNORE_UNUSED' flagxingyu.wu3-52/+52
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-05-15clktree: jh7110: disable jh7110_clk_disable function interface.samin1-2/+2
/*do not upstram*/ The system will hang when clk_disable. need to debug. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-28clk:starfive: Add definition instead of numbersxingyu.wu5-195/+230
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-28clk:starfive: Add isp clock tree driverxingyu.wu4-0/+296
Clock references refer to include/dt-bindings/clock/starfive-jh7110-isp.h Enable the isp clock tree driver in dts file if use it. If the fpga is not connetted with isp board, the isp clock tree must be disabled. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-24risv:dts:starfive:Add timer clocktreexingyu.wu1-5/+5
1.Modify the clock tree driver to make timer clock ignore disabled_unused. 2.Add different 'clock-frequency' node in fpga, evb and visionfive dts file. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-04-19clk:starfive: Adjust the formatxingyu.wu6-526/+526
Adjust and modify the clock driver's format Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-13arch:riscv:Kconfig: Add choice with SOC board typexingyu.wu5-24/+26
Add config about user can choose the board type about FPGA, EVB or Visionfive Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-13clk:starfive: Add vout clock tree driverxingyu.wu4-0/+281
Clock references refer to include/dt-bindings/clock/starfive-jh7110-vout.h Change the value about 'status' of clkvout node in dts file when want to use vout clock. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-13clk:starfive: Add JH7110 clock tree driver for kernel 5.15xingyu.wu9-0/+1643
Add clock driver about sys, stg and aon clock for JH7110. Clock references refer to include/dt-bindings/clock/starfive-jh7110-clkgen.h Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2021-10-30Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds1-5/+5
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fix from Stephen Boyd: "One fix for the composite clk that broke when we changed this clk type to use the determine_rate instead of round_rate clk op by default. This caused lots of problems on Rockchip SoCs because they heavily use the composite clk code to model the clk tree" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: composite: Also consider .determine_rate for rate + mux composites
2021-10-18clk: composite: Also consider .determine_rate for rate + mux compositesMartin Blumenstingl1-5/+5
Commit 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") switches clk_divider_ops to implement .determine_rate by default. This breaks composite clocks with multiple parents because clk-composite.c does not use the special handling for mux + divider combinations anymore (that was restricted to rate clocks which only implement .round_rate, but not .determine_rate). Alex reports: This breaks lot of clocks for Rockchip which intensively uses composites, i.e. those clocks will always stay at the initial parent, which in some cases is the XTAL clock and I strongly guess it is the same for other platforms, which use composite clocks having more than one parent (e.g. mediatek, ti ...) Example (RK3399) clk_sdio is set (initialized) with XTAL (24 MHz) as parent in u-boot. It will always stay at this parent, even if the mmc driver sets a rate of 200 MHz (fails, as the nature of things), which should switch it to any of its possible parent PLLs defined in mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p (see clk-rk3399.c) - which never happens. Restore the original behavior by changing the priority of the conditions inside clk-composite.c. Now the special rate + mux case (with rate_ops having a .round_rate - which is still the case for the default clk_divider_ops) is preferred over rate_ops which have .determine_rate defined (and not further considering the mux). Fixes: 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") Reported-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20211016105022.303413-2-martin.blumenstingl@googlemail.com Tested-by: Alex Bee <knaerzche@gmail.com> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: add select QCOM_GDSC for SM6350Luca Weiss1-0/+1
QCOM_GDSC is needed for the gcc driver to probe. Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20211007212444.328034-2-luca@z3ntu.xyz Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-sm6115: Fix offset for hlos1_vote_turing_mmu_tbu0_gdscShawn Guo1-1/+1
It looks that the offset 0x7d060 is a copy & paste from above hlos1_vote_turing_mmu_tbu1_gdsc. Correct it to 0x7d07c as per downstream kernel. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210919022308.24046-1-shawn.guo@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-29Merge tag 'renesas-clk-for-v5.15-tag3' of ↵Stephen Boyd2-1/+3
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-fixes Pull Renesas clk driver fixes from Geert Uytterhoeven: - Fix inverted logic in RZ/G2L .is_enabled() function * tag 'renesas-clk-for-v5.15-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rzg2l: Fix clk status function clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
2021-09-25clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen1-9/+0
Remove the duplicate s2f_user0_clk and the unused s2f_usr0_mux define. Fixes: f817c132db67 ("clk: socfpga: agilex: fix up s2f_user0_clk representation") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210916225126.1427700-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-03 00:53:57 +0300