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2018-03-19clk: bcm2835: Protect sections updating shared registersBoris Brezillon1-0/+4
CM_PLLx and A2W_XOSC_CTRL registers are accessed by different clock handlers and must be accessed with ->regs_lock held. Update the sections where this protection is missing. Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: <stable@vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19clk: bcm2835: Fix ana->maskX definitionsBoris Brezillon1-4/+4
ana->maskX values are already '~'-ed in bcm2835_pll_set_rate(). Remove the '~' in the definition to fix ANA setup. Note that this commit fixes a long standing bug preventing one from using an HDMI display if it's plugged after the FW has booted Linux. This is because PLLH is used by the HDMI encoder to generate the pixel clock. Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: <stable@vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-15clk: aspeed: Prevent reset if clock is enabledEddie James1-12/+17
According to the Aspeed specification, the reset and enable sequence should be done when the clock is stopped. The specification doesn't define behavior if the reset is done while the clock is enabled. From testing on the AST2500, the LPC Controller has problems if the clock is reset while enabled. Therefore, check whether the clock is enabled or not before performing the reset and enable sequence in the Aspeed clock driver. Reported-by: Lei Yu <mine260309@gmail.com> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks") Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-15clk: aspeed: Fix is_enabled for certain clocksEddie James1-1/+2
Some of the Aspeed clocks are disabled by setting the relevant bit in the "clock stop control" register to one, while others are disabled by setting their bit to zero. The driver already uses a flag per gate to identify this behavior, but doesn't apply it in the clock is_enabled function. Use the existing gate flag to correctly return whether or not a clock is enabled in the aspeed_clk_is_enabled function. Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Fixes: 6671507f0fbd ("clk: aspeed: Handle inverse polarity of USB port 1 clock gate") Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-13clk: qcom: msm8916: Fix return value check in qcom_apcs_msm8916_clk_probe()Wei Yongjun1-3/+2
In case of error, the function dev_get_regmap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 81ac38847a1d ("clk: qcom: Add APCS clock controller support") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-13clk: hisilicon: hi3660：Fix potential NULL dereference in ↵Wei Yongjun1-0/+2
hi3660_stub_clk_probe() platform_get_resource() may return NULL, add proper check to avoid potential NULL dereferencing. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Fixes: 4f16f7ff3bc0 ("clk: hisilicon: Add support for Hi3660 stub clocks") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-13Merge branch 'clk-helpers' (early part) into clk-fixesStephen Boyd1-1/+3
* 'clk-helpers' (early part): clk: fix determine rate error with pass-through clock
2018-03-13clk: fix determine rate error with pass-through clockJerome Brunet1-1/+3
If we try to determine the rate of a pass-through clock (a clock which does not implement .round_rate() nor .determine_rate()), clk_core_round_rate_nolock() will directly forward the call to the parent clock. In the particular case where the pass-through actually does not have a parent, clk_core_round_rate_nolock() will directly return 0 with the requested rate still set to the initial request structure. This is interpreted as if the rate could be exactly achieved while it actually cannot be adjusted. This become a real problem when this particular pass-through clock is the parent of a mux with the flag CLK_SET_RATE_PARENT set. The pass-through clock will always report an exact match, get picked and finally error when the rate is actually getting set. This is fixed by setting the rate inside the req to 0 when core is NULL in clk_core_round_rate_nolock() (same as in __clk_determine_rate() when hw is NULL) Fixes: 0f6cc2b8e94d ("clk: rework calls to round and determine rate callbacks") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-13Merge branch 'clk-phase' into clk-fixesStephen Boyd1-1/+4
* clk-phase: clk: update cached phase to respect the fact when setting phase
2018-03-13Merge tag 'ti-clk-fixes-4.16' of https://github.com/t-kristo/linux-pm into ↵Stephen Boyd3-2/+4
clk-fixes Pull TI SoC clock fixes for 4.16 from Tero Kristo: * tag 'ti-clk-fixes-4.16' of https://github.com/t-kristo/linux-pm: clk: ti: am43xx: add set-rate-parent support for display clkctrl clock clk: ti: am33xx: add set-rate-parent support for display clkctrl clock clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
2018-03-13Merge tag 'clk-imx-fixes-4.16' of ↵Stephen Boyd1-3/+17
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes Pull i.MX clock fixes for 4.16 from Shawn Guo: - Update i.MX5 clock driver to register UART4/5 clock only on i.MX50 and i.MX53. It fixes a kernel warning seen on i.MX53, caused by commit 59dc3d8c8673 ("clk: imx51: uart4, uart5 gates only exist on imx50, imx53"). * tag 'clk-imx-fixes-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx51-imx53: Fix UART4/5 registration on i.MX50 and i.MX53
2018-03-13Merge tag 'sunxi-clk-fixes-for-4.16' of ↵Stephen Boyd1-3/+3
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull Allwinner clock fixes for 4.16 from Chen-Yu Tsai: A critical fix for the A31 sunxi-ng clock driver. The CLK_OUT clocks had definitions paired with the incorrect type of clk ops. This results in a serious oops starting with commit 946797aa3f08 ("clk: sunxi-ng: Support fixed post-dividers on MP style clocks"), which exposed the incorrect clk ops when it added a new field to the data structures, which then nudged the underlying (compatible but incorrect) data structures out of alignment. * tag 'sunxi-clk-fixes-for-4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops
2018-03-12clk: migrate the count of orphaned clocks at initJerome Brunet1-16/+21
The orphan clocks reparents should migrate any existing count from the orphan clock to its new acestor clocks, otherwise we may have inconsistent counts in the tree and end-up with gated critical clocks Assuming we have two clocks, A and B. * Clock A has CLK_IS_CRITICAL flag set. * Clock B is an ancestor of A which can gate. Clock B gate is left enabled by the bootloader. Step 1: Clock A is registered. Since it is a critical clock, it is enabled. The clock being still an orphan, no parent are enabled. Step 2: Clock B is registered and reparented to clock A (potentially through several other clocks). We are now in situation where the enable count of clock A is 1 while the enable count of its ancestors is 0, which is not good. Step 3: in lateinit, clk_disable_unused() is called, the enable_count of clock B being 0, clock B is gated and and critical clock A actually gets disabled. This situation was found while adding fdiv_clk gates to the meson8b platform. These clocks parent clk81 critical clock, which is the mother of all peripheral clocks in this system. Because of the issue described here, the system is crashing when clk_disable_unused() is called. The situation is solved by reverting commit f8f8f1d04494 ("clk: Don't touch hardware when reparenting during registration"). To avoid breaking again the situation described in this commit description, enabling critical clock should be done before walking the orphan list. This way, a parent critical clock may not be accidentally disabled due to the CLK_OPS_PARENT_ENABLE mechanism. Fixes: f8f8f1d04494 ("clk: Don't touch hardware when reparenting during registration") Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-12clk: update cached phase to respect the fact when setting phaseShawn Lin1-1/+4
It's found that the final phase set by driver doesn't match that of the output from clk_summary: dwmmc_rockchip fe310000.dwmmc: Successfully tuned phase to 346 mmc0: new ultra high speed SDR104 SDIO card at address 0001 cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample sdio_sample 0 1 0 50000000 0 0 It seems the cached core->phase isn't updated after the clk was registered. So fix this issue by updating the core->phase if setting phase successfully. Fixes: 9e4d04adeb1a ("clk: add clk_core_set_phase_nolock function") Cc: Stable <stable@vger.kernel.org> Cc: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2018-03-08clk: ti: am43xx: add set-rate-parent support for display clkctrl clockTero Kristo1-1/+1
Display driver assumes it can use clk_set_rate for the display clock via set-rate-parent mechanism, so add the flag for this to id. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2018-03-08clk: ti: am33xx: add set-rate-parent support for display clkctrl clockTero Kristo1-1/+1
Display driver assumes it can use clk_set_rate for the display clock via set-rate-parent mechanism, so add the flag for this to it. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Jyri Sarha <jsarha@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Jyri Sarha <jsarha@ti.com>
2018-03-08clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flagTero Kristo1-0/+2
Certain clkctrl clocks, notably the display ones, use the CLK_SET_RATE_PARENT feature extensively. Add support for this flag to the clkctrl clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Jyri Sarha <jsarha@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Jyri Sarha <jsarha@ti.com>
2018-02-22clk: imx51-imx53: Fix UART4/5 registration on i.MX50 and i.MX53Fabio Estevam1-3/+17
Since commit 59dc3d8c8673 ("clk: imx51: uart4, uart5 gates only exist on imx50, imx53") the following warnings are seen on i.MX53: [ 2.776190] ------------[ cut here ]------------ [ 2.780948] WARNING: CPU: 0 PID: 1 at ../drivers/clk/clk.c:811 clk_core_disable+0xc4/0xe0 [ 2.789145] Modules linked in: [ 2.792236] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.15.0-rc7-next-20180115 #1 [ 2.799735] Hardware name: Freescale i.MX53 (Device Tree Support) [ 2.805845] Backtrace: [ 2.808329] [<c010d1a0>] (dump_backtrace) from [<c010d460>] (show_stack+0x18/0x1c) [ 2.815919] r7:00000000 r6:60000093 r5:00000000 r4:c10798d4 [ 2.821607] [<c010d448>] (show_stack) from [<c0a353ec>] (dump_stack+0xb4/0xe8) [ 2.828854] [<c0a35338>] (dump_stack) from [<c0126144>] (__warn+0xf0/0x11c) [ 2.835837] r9:00000000 r8:0000032b r7:00000009 r6:c0d429f8 r5:00000000 r4:00000000 [ 2.843601] [<c0126054>] (__warn) from [<c0126288>] (warn_slowpath_null+0x44/0x50) [ 2.851191] r8:c1008908 r7:c0e08874 r6:c04bfac8 r5:0000032b r4:c0d429f8 [ 2.857913] [<c0126244>] (warn_slowpath_null) from [<c04bfac8>] (clk_core_disable+0xc4/0xe0) [ 2.866369] r6:dc02bb00 r5:dc02a980 r4:dc02a980 [ 2.871011] [<c04bfa04>] (clk_core_disable) from [<c04c0e54>] (clk_core_disable_lock+0x20/0x2c) [ 2.879726] r5:dc02a980 r4:80000013 [ 2.883323] [<c04c0e34>] (clk_core_disable_lock) from [<c04c0e84>] (clk_disable+0x24/0x28) [ 2.891604] r5:c0f6b3e4 r4:0000001c [ 2.895209] [<c04c0e60>] (clk_disable) from [<c0f2340c>] (imx_clk_disable_uart+0x50/0x68) [ 2.903412] [<c0f233bc>] (imx_clk_disable_uart) from [<c010277c>] (do_one_initcall+0x50/0x19c) [ 2.912043] r7:c0e08874 r6:c0f63854 r5:c0f233bc r4:ffffe000 [ 2.917726] [<c010272c>] (do_one_initcall) from [<c0f00f00>] (kernel_init_freeable+0x118/0x1d0) [ 2.926447] r9:c0f63858 r8:000000f0 r7:c0e08874 r6:c0f63854 r5:c107b500 r4:c0f75260 [ 2.934220] [<c0f00de8>] (kernel_init_freeable) from [<c0a4a5f0>] (kernel_init+0x10/0x118) [ 2.942506] r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0a4a5e0 [ 2.950351] r4:00000000 [ 2.952908] [<c0a4a5e0>] (kernel_init) from [<c01010b4>] (ret_from_fork+0x14/0x20) [ 2.960496] Exception stack(0xdc05dfb0 to 0xdc05dff8) [ 2.965569] dfa0: 00000000 00000000 00000000 00000000 [ 2.973768] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 2.981965] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 2.988596] r5:c0a4a5e0 r4:00000000 [ 2.992188] ---[ end trace 346e26f708876edd ]--- [ 2.997420] ------------[ cut here ]------------ In order to fix the problem UART4/5 registration needs to happen only on i.MX50 and i.MX53. So let mx51_clocks_init() register only UART1-3 and mx50_clocks_init()/mx53_clocks_init register all the UART1-5 ports. Fixes: 59dc3d8c8673 ("clk: imx51: uart4, uart5 gates only exist on imx50, imx53") Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-19clk: sunxi-ng: a31: Fix CLK_OUT_* clock opsChen-Yu Tsai1-3/+3
When support for the A31/A31s CCU was first added, the clock ops for the CLK_OUT_* clocks was set to the wrong type. The clocks are MP-type, but the ops was set for div (M) clocks. This went unnoticed until now. This was because while they are different clocks, their data structures aligned in a way that ccu_div_ops would access the second ccu_div_internal and ccu_mux_internal structures, which were valid, if not incorrect. Furthermore, the use of these CLK_OUT_* was for feeding a precise 32.768 kHz clock signal to the WiFi chip. This was achievable by using the parent with the same clock rate and no divider. So the incorrect divider setting did not affect this usage. Commit 946797aa3f08 ("clk: sunxi-ng: Support fixed post-dividers on MP style clocks") added a new field to the ccu_mp structure, which broke the aforementioned alignment. Now the system crashes as div_ops tries to look up a nonexistent table. Reported-by: Philipp Rossak <embed3d@gmail.com> Tested-by: Philipp Rossak <embed3d@gmail.com> Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Cc: <stable@vger.kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-02-07Merge tag 'mips_4.16' of ↵Linus Torvalds5-18/+566
git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips Pull MIPS updates from James Hogan: "These are the main MIPS changes for 4.16. Rough overview: (1) Basic support for the Ingenic JZ4770 based GCW Zero open-source handheld video game console (2) Support for the Ranchu board (used by Android emulator) (3) Various cleanups and misc improvements More detailed summary: Fixes: - Fix generic platform's USB_*HCI_BIG_ENDIAN selects (4.9) - Fix vmlinuz default build when ZBOOT selected - Fix clean up of vmlinuz targets - Fix command line duplication (in preparation for Ingenic JZ4770) Miscellaneous: - Allow Processor ID reads to be to be optimised away by the compiler (improves performance when running in guest) - Push ARCH_MIGHT_HAVE_PC_SERIO/PARPORT down to platform level to disable on generic platform with Ranchu board support - Add helpers for assembler macro instructions for older assemblers - Use assembler macro instructions to support VZ, XPA & MSA operations on older assemblers, removing C wrapper duplication - Various improvements to VZ & XPA assembly wrappers - Add drivers/platform/mips/ to MIPS MAINTAINERS entry Minor cleanups: - Misc FPU emulation cleanups (removal of unnecessary include, moving macros to common header, checkpatch and sparse fixes) - Remove duplicate assignment of core in play_dead() - Remove duplication in watchpoint handling - Remove mips_dma_mapping_error() stub - Use NULL instead of 0 in prepare_ftrace_return() - Use proper kernel-doc Return keyword for __compute_return_epc_for_insn() - Remove duplicate semicolon in csum_fold() Platform support: Broadcom: - Enable ZBOOT on BCM47xx Generic platform: - Add Ranchu board support, used by Android emulator - Fix machine compatible string matching for Ranchu - Support GIC in EIC mode Ingenic platforms: - Add DT, defconfig and other support for JZ4770 SoC and GCW Zero - Support dynamnic machine types (i.e. JZ4740 / JZ4770 / JZ4780) - Add Ingenic JZ4770 CGU clocks - General Ingenic clk changes to prepare for JZ4770 SoC support - Use common command line handling code - Add DT vendor prefix to GCW (Game Consoles Worldwide) Loongson: - Add MAINTAINERS entry for Loongson2 and Loongson3 platforms - Drop 32-bit support for Loongson 2E/2F devices - Fix build failures due to multiple use of 'MEM_RESERVED'" * tag 'mips_4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (53 commits) MIPS: Malta: Sanitize mouse and keyboard configuration. MIPS: Update defconfigs after previous patch. MIPS: Push ARCH_MIGHT_HAVE_PC_SERIO down to platform level MIPS: Push ARCH_MIGHT_HAVE_PC_PARPORT down to platform level MIPS: SMP-CPS: Remove duplicate assignment of core in play_dead MIPS: Generic: Support GIC in EIC mode MIPS: generic: Fix Makefile alignment MIPS: generic: Fix ranchu_of_match[] termination MIPS: generic: Fix machine compatible matching MIPS: Loongson fix name confict - MEM_RESERVED MIPS: bcm47xx: enable ZBOOT support MIPS: Fix trailing semicolon MIPS: Watch: Avoid duplication of bits in mips_read_watch_registers MIPS: Watch: Avoid duplication of bits in mips_install_watch_registers. MIPS: MSA: Update helpers to use new asm macros MIPS: XPA: Standardise readx/writex accessors MIPS: XPA: Allow use of $0 (zero) to MTHC0 MIPS: XPA: Use XPA instructions in assembly MIPS: VZ: Pass GC0 register names in $n format MIPS: VZ: Update helpers to use new asm macros ...
2018-02-02Merge tag 'clk-for-linus' of ↵Linus Torvalds105-5767/+11752
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework has a handful of patches this time around, mostly due to the clk rate protection support added by Jerome Brunet. This feature will allow consumers to lock in a certain rate on the output of a clk so that things like audio playback don't hear pops when the clk frequency changes due to shared parent clks changing rates. Currently the clk API doesn't guarantee the rate of a clk stays at the rate you request after clk_set_rate() is called, so this new API will allow drivers to express that requirement. Beyond this, the core got some debugfs pretty printing patches and a couple minor non-critical fixes. Looking outside of the core framework diff we have some new driver additions and the removal of a legacy TI clk driver. Both of these hit high in the dirstat. Also, the removal of the asm-generic/clkdev.h file causes small one-liners in all the architecture Kbuild files. Overall, the driver diff seems to be the normal stuff that comes all the time to fix little problems here and there and to support new hardware. Summary: Core: - Clk rate protection - Symbolic clk flags in debugfs output - Clk registration enabled clks while doing bookkeeping updates New Drivers: - Spreadtrum SC9860 - HiSilicon hi3660 stub - Qualcomm A53 PLL, SPMI clkdiv, and MSM8916 APCS - Amlogic Meson-AXG - ASPEED BMC Removed Drivers: - TI OMAP 3xxx legacy clk (non-DT) support - asm*/clkdev.h got removed (not really a driver) Updates: - Renesas FDP1-0 module clock on R-Car M3-W - Renesas LVDS module clock on R-Car V3M - Misc fixes to pr_err() prints - Qualcomm MSM8916 audio fixes - Qualcomm IPQ8074 rounded out support for more peripherals - Qualcomm Alpha PLL variants - Divider code was using container_of() on bad pointers - Allwinner DE2 clks on H3 - Amlogic minor data fixes and dropping of CLK_IGNORE_UNUSED - Mediatek clk driver compile test support - AT91 PMC clk suspend/resume restoration support - PLL issues fixed on si5351 - Broadcom IProc PLL calculation updates - DVFS support for Armada mvebu CPU clks - Allwinner fixed post-divider support - TI clkctrl fixes and support for newer SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits) clk: aspeed: Handle inverse polarity of USB port 1 clock gate clk: aspeed: Fix return value check in aspeed_cc_init() clk: aspeed: Add reset controller clk: aspeed: Register gated clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register core clocks clk: Add clock driver for ASPEED BMC SoCs clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built clk: fix reentrancy of clk_enable() on UP systems clk: meson-axg: fix potential NULL dereference in axg_clkc_probe() clk: Simplify debugfs registration clk: Fix debugfs_create_*() usage clk: Show symbolic clock flags in debugfs clk: renesas: r8a7796: Add FDP clock clk: Move __clk_{get,put}() into private clk.h API clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks clk: Improve flags doc for of_clk_detect_critical() arch: Remove clkdev.h asm-generic from Kbuild clk: sunxi-ng: a83t: Add M divider to TCON1 clock clk: Prepare to remove asm-generic/clkdev.h ...
2018-02-02Merge tag 'armsoc-dt' of ↵Linus Torvalds14-1052/+2053
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Arnd Bergmann: "We get a moderate number of new machines this time, and only one new SoC variant (Actions S700): Actions: - S700 Soc and CubieBoard7 development board - Allo.com Sparky Single-board-computer Allwinner: - Orange Pi R1 development board - Libre Computer Board ALL-H3-CC H3 single-board computer ASpeed ast2x00: - Witherspoon: OpenPower Power9 server manufactured by IBM that uses the ASPEED ast2500 - Zaius: OpenPower Power9 server manufactured by Invatech that uses the ASPEED ast2500 - Q71L: Intel Xeon server manufactured by Qanta that uses the ASPEED ast2400 AT91: - Axentia Nattis/Natte digital signage - sama5d2 PTC-ek Evaluation board Freescale/NXP i.MX: - SolidRun Humminboard2 development board - Variscite DART-MX6 SoM and Carrier-board - Technologic TS-4600 and TS-7970 development board - Toradex Colibri iMX7D SoM board - v1.5 variant of Solidrun Cubox-i and Hummingboard Freescale/NXP Layerscape: - Moxa UC-8410A Series industrial computer Gemini: - D-Link DNS-313 NAS enclosure OMAP: - LogicPD OMAP35xx SOM-LV devkit - LogicPD OMAP35xx Torpedo devkit Renesas: - r8a77970 (V3M) Starter Kit board - r8a7795 (M3-W) Salvator-XS board We finally managed to get the dtc warnings under control, with no more build-time warnings for bad device tree files. This includes fixes for the majority of platforms, including nomadik, samsung, lpc32xx, STi, spear, mediatek, freescale, qcom, realview, keystone, omap, kirkwood, renesas, hisilicon, and broadcom. Files get rearranged on a few platforms, in particular the Marvell Armada 7K/8K device tree files are changed in preparation for future SoC support, based on more than two of the same chips in one package, and some boards get renamed for oxnas for consistency. Finally, many existing SoCs gain descriptions for additional on-chip devices that we can now support with kernel drivers: - Allwinner A83t (drm, ethernet, i2c, ...), H3/H5 (USB-OTG) - Amlogic AXG family (clk, pinctrl, pwm, ...), and others (vpu, hdmi) - Aspeed clk controller support - Freescale LS1088A, LS1021A device support - Gemini Ethernet, PCI, TVE, panel - Keystone gpio, qspi, more uarts - Mediatek cpufreq, regulator, clock, reset - Marvell thermal, cpufreq, nand - Renesas SMP, thermal, timer, PWM, sound, phy, ipmmu - Rockchip Mipi, GPU, display - Samsung Exynos5433 PMU, power domain, nfc - Spreadtrum: sc9860 clocks - Tegra TX2 PSDI, HDMI, I2C,SMMU, display, fuse, ..." * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (690 commits) arm64: dts: stratix10: fix SPI settings ARM: dts: socfpga: add i2c reset signals arm64: dts: stratix10: add USB ECC reset bit arm64: dts: stratix10: enable USB on the devkit ARM: dts: socfpga: disable over-current for Arria10 USB devkit ARM: dts: Nokia N9: add support for up/down keys in the dts ARM: dts: nomadik: add interrupt-parent for clcd ARM: dts: Add ethernet to a bunch of platforms ARM: dts: Add ethernet to the Gemini SoC ARM: dts: rename oxnas dts files ARM: dts: s5pv210: add interrupt-parent for ohci ARM: lpc3250: fix uda1380 gpio numbers ARM: dts: STi: Add gpio polarity for "hdmi,hpd-gpio" property ARM: dts: dra7: Reduce shut down temperature of non-cpu thermal zones ARM: dts: n900: Add aliases for lcd and tvout displays ARM: dts: Update ti-sysc data for existing users ARM: dts: Fix smartreflex compatible for omap3 shared mpu-iva instance arm64: dts: marvell: armada-80x0: Fix pinctrl compatible string arm: spear13xx: Fix spics gpio controller's warning arm: spear13xx: Fix dmas cells ...
2018-01-27Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and ↵Stephen Boyd15-104/+929
'clk-allwinner' into clk-next * clk-aspeed: clk: aspeed: Handle inverse polarity of USB port 1 clock gate clk: aspeed: Fix return value check in aspeed_cc_init() clk: aspeed: Add reset controller clk: aspeed: Register gated clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register core clocks clk: Add clock driver for ASPEED BMC SoCs dt-bindings: clock: Add ASPEED constants * clk-lock-UP: clk: fix reentrancy of clk_enable() on UP systems * clk-mediatek: clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built clk: mediatek: Fix all warnings for missing struct clk_onecell_data clk: mediatek: fixup test-building of MediaTek clock drivers clk: mediatek: group drivers under indpendent menu * clk-allwinner: clk: sunxi-ng: a83t: Add M divider to TCON1 clock clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU clk: sunxi-ng: add support for Allwinner H3 DE2 CCU dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3 clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL clk: sunxi-ng: Support fixed post-dividers on NM style clocks clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: Support fixed post-dividers on MP style clocks clk: sunxi: Use PTR_ERR_OR_ZERO()
2018-01-27Merge branches 'clk-remove-asm-clkdev', 'clk-debugfs-fixes', 'clk-renesas' ↵Stephen Boyd21-163/+1276
and 'clk-meson' into clk-next * clk-remove-asm-clkdev: clk: Move __clk_{get,put}() into private clk.h API clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks arch: Remove clkdev.h asm-generic from Kbuild clk: Prepare to remove asm-generic/clkdev.h blackfin: Use generic clkdev.h header * clk-debugfs-fixes: clk: Simplify debugfs registration clk: Fix debugfs_create_*() usage clk: Show symbolic clock flags in debugfs clk: Improve flags doc for of_clk_detect_critical() * clk-renesas: clk: renesas: r8a7796: Add FDP clock clk: renesas: cpg-mssr: Keep wakeup sources active during system suspend clk: renesas: mstp: Keep wakeup sources active during system suspend clk: renesas: r8a77970: Add LVDS clock * clk-meson: clk: meson-axg: fix potential NULL dereference in axg_clkc_probe() clk: meson-axg: make local symbol axg_gp0_params_table static clk: meson-axg: fix return value check in axg_clkc_probe() clk: meson: mpll: use 64-bit maths in params_from_rate clk: meson-axg: add clock controller drivers clk: meson-axg: add clocks dt-bindings required header dt-bindings: clock: add compatible variant for the Meson-AXG clk: meson: make the spinlock naming more specific clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks clk: meson: gxbb: fix wrong clock for SARADC/SANA
2018-01-27Merge branch 'clk-divider-container' into clk-nextStephen Boyd6-9/+9
* clk-divider-container: clk: divider: fix incorrect usage of container_of Plus fixup sprd/div.c to pass the width too.
2018-01-27Merge branches 'clk-iproc', 'clk-mvebu' and 'clk-qcom-a53' into clk-nextStephen Boyd10-102/+737
* clk-iproc: clk: iproc: Minor tidy up of iproc pll data structures clk: iproc: Allow plls to do minor rate changes without reset clk: iproc: Fix error in the pll post divider rate calculation clk: iproc: Allow iproc pll to runtime calculate vco parameters * clk-mvebu: clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO() * clk-qcom-a53: clk: qcom: Add APCS clock controller support clk: qcom: Add regmap mux-div clocks support clk: qcom: Add A53 PLL support
2018-01-27Merge branches 'clk-at91', 'clk-imx7ulp', 'clk-axigen', 'clk-si5351' and ↵Stephen Boyd7-41/+146
'clk-pxa' into clk-next * clk-at91: clk: at91: pmc: Support backup for programmable clocks clk: at91: pmc: Save SCSR during suspend clk: at91: pmc: Wait for clocks when resuming * clk-imx7ulp: clk: Don't touch hardware when reparenting during registration * clk-axigen: clk: axi-clkgen: Round closest in round_rate() and recalc_rate() clk: axi-clkgen: Correctly handle nocount bit in recalc_rate() * clk-si5351: clk: si5351: _si5351_clkout_reset_pll() can be static clk: si5351: Do not enable parent clocks on probe clk: si5351: Rename internal plls to avoid name collisions clk: si5351: Apply PLL soft reset before enabling the outputs clk: si5351: Add DT property to enable PLL reset clk: si5351: implement remove handler * clk-pxa: clk: pxa: unbreak lookup of CLK_POUT
2018-01-27Merge branches 'clk-spreadtrum', 'clk-mvebu-dvfs', 'clk-qoriq', 'clk-imx' ↵Stephen Boyd29-81/+7213
and 'clk-qcom-ipq8074' into clk-next * clk-spreadtrum: clk: sprd: add clocks support for SC9860 clk: sprd: Add dt-bindings include file for SC9860 dt-bindings: Add Spreadtrum clock binding documentation clk: sprd: add adjustable pll support clk: sprd: add composite clock support clk: sprd: add divider clock support clk: sprd: add mux clock support clk: sprd: add gate clock support clk: sprd: Add common infrastructure clk: move clock common macros out from vendor directories * clk-mvebu-dvfs: clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS clk: mvebu: armada-37xx-periph: cosmetic changes * clk-qoriq: clk: qoriq: add more divider clocks support * clk-imx: clk: imx51: uart4, uart5 gates only exist on imx50, imx53 * clk-qcom-ipq8074: clk: qcom: ipq8074: add misc resets for PCIE and NSS dt-bindings: clock: qcom: add misc resets for PCIE and NSS clk: qcom: ipq8074: add GP and Crypto clocks clk: qcom: ipq8074: add NSS ethernet port clocks clk: qcom: ipq8074: add NSS clocks clk: qcom: ipq8074: add PCIE, USB and SDCC clocks clk: qcom: ipq8074: add remaining PLL’s dt-bindings: clock: qcom: add remaining clocks for IPQ8074 clk: qcom: ipq8074: fix missing GPLL0 divider width clk: qcom: add parent map for regmap mux clk: qcom: add read-only divider operations
2018-01-27Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' ↵Stephen Boyd15-5241/+918
and 'clk-omap' into clk-next * clk-qcom-alpha-pll: clk: qcom: add read-only alpha pll post divider operations clk: qcom: support for 2 bit PLL post divider clk: qcom: support Brammo type Alpha PLL clk: qcom: support Huayra type Alpha PLL clk: qcom: support for dynamic updating the PLL clk: qcom: support for alpha mode configuration clk: qcom: flag for 64 bit CONFIG_CTL clk: qcom: fix 16 bit alpha support calculation clk: qcom: support for alpha pll properties * clk-check-ops-ptr: clk: check ops pointer on clock register * clk-protect-rate: clk: fix set_rate_range when current rate is out of range clk: add clk_rate_exclusive api clk: cosmetic changes to clk_summary debugfs entry clk: add clock protection mechanism to clk core clk: use round rate to bail out early in set_rate clk: rework calls to round and determine rate callbacks clk: add clk_core_set_phase_nolock function clk: take the prepare lock out of clk_core_set_parent clk: fix incorrect usage of ENOSYS * clk-omap: clk: ti: Drop legacy clk-3xxx-legacy code
2018-01-27clk: aspeed: Handle inverse polarity of USB port 1 clock gateBenjamin Herrenschmidt1-3/+12
The USB port 1 clock gate control has an inversed polarity from all the other clock gates in the chip. This makes the aspeed_clk_{enable,disable} functions honor the flag CLK_GATE_SET_TO_DISABLE and set that flag appropriately so it's set for all clocks except USB port 1. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-27clk: aspeed: Fix return value check in aspeed_cc_init()Wei Yongjun1-1/+1
In case of error, the function of_iomap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: a2e230c7b2ea ("clk: Add clock driver for ASPEED BMC SoCs") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-27clk: aspeed: Add reset controllerJoel Stanley1-1/+81
There are some resets that are not associated with gates. These are represented by a reset controller. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-27clk: aspeed: Register gated clocksJoel Stanley1-0/+130
The majority of the clocks in the system are gates paired with a reset controller that holds the IP in reset. This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: 1. Place IP in reset 2. Enable clock 3. Delay 4. Release reset There are some gates that do not have an associated reset; these are handled by using -1 as the index for the reset. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-27clk: aspeed: Add platform driver and register PLLsJoel Stanley1-0/+130
This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-27clk: aspeed: Register core clocksJoel Stanley1-0/+177
This registers the core clocks; those which are required to calculate the rate of the timer peripheral so the system can load a clocksource driver. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-27clk: Add clock driver for ASPEED BMC SoCsJoel Stanley3-0/+154
This adds the stub of a driver for the ASPEED SoCs. The clocks are defined and the static registration is set up. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-19clk: Add Ingenic jz4770 CGU driverPaul Cercueil2-0/+484
Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-19clk: ingenic: Add code to enable/disable PLLsPaul Cercueil1-15/+74
This commit permits the PLLs to be dynamically enabled and disabled when their children clocks are enabled and disabled. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18480/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-19clk: ingenic: support PLLs with no bypass bitPaul Cercueil2-1/+4
The second PLL of the JZ4770 does not have a bypass bit. This commit makes it possible to support it with the current common CGU code. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18479/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-19clk: ingenic: Fix recalc_rate for clocks with fixed dividerPaul Cercueil1-0/+2
Previously, the clocks with a fixed divider would report their rate as being the same as the one of their parent, independently of the divider in use. This commit fixes this behaviour. This went unnoticed as neither the jz4740 nor the jz4780 CGU code have clocks with fixed dividers yet. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18477/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-19clk: ingenic: Use const pointer to clk_ops in structPaul Cercueil2-2/+2
The CGU common code does not modify the pointed clk_ops structure, so it should be marked as const. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18476/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-11clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being builtSean Wang3-9/+2
Changes from v1->v2: Add 'select RESET_CONTROLLER' under COMMON_CLK_MEDIATEK and enable reset.c to be built when COMMON_CLK_MEDIATEK is selected. That should be quite reasonable because the reset controller is tightly embedded inside and exported from these clock subsystems. At least it can be found on infracfg and pericfg subsystem that both are really fundamental block lots of devices must depend on. commit 74cb0d6dde8 ("clk: mediatek: fixup test-building of MediaTek clock drivers") can let the build system looking into the directory where the clock drivers resides and then allow test-building the drivers. But the change also gives rise to certain incorrect behavior which is reset.c being built even not depending on either COMPILE_TEST or ARCH_MEDIATEK alternative dependency. To get rid of reset.c being built unexpectedly on the other platforms, it would be a good change that the file should be built depending on its own specific configuration rather than just on generic RESET_CONTROLLER one. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: Jean Delvare <jdelvare@suse.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-11clk: fix reentrancy of clk_enable() on UP systemsDavid Lechner1-1/+9
Reentrant calls to clk_enable() are not working on UP systems. This is caused by the fact spin_trylock_irqsave() always returns true when CONFIG_SMP=n (and CONFIG_DEBUG_SPINLOCK=n) which causes the reference counting to not work correctly when clk_enable_lock() is called twice before clk_enable_unlock() is called (this happens when clk_enable() is called from within another clk_enable()). This fixes the problem by skipping the call to spin_trylock_irqsave() on UP systems and relying solely on reference counting. We also make sure to set flags in this case so that we are not returning an uninitialized value. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-11clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()weiyongjun (A)1-0/+2
platform_get_resource() may return NULL, add proper check to avoid potential NULL dereferencing. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-11clk: Simplify debugfs registrationStephen Boyd1-6/+2
We don't need a goto here. Drop it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-11clk: Fix debugfs_create_*() usageGeert Uytterhoeven1-19/+17
When exposing data access through debugfs, the correct debugfs_create_*() functions must be used, matching the data types. Remove all casts from data pointers passed to debugfs_create_*() functions, as such casts prevent the compiler from flagging bugs. clk_core.rate and .accuracy are "unsigned long", hence casting their addresses to "u32 *" exposed the wrong halves on big-endian 64-bit systems. Fix this by using debugfs_create_ulong() instead. Octal permissions are preferred, as they are easier to read than symbolic permissions. Hence replace "S_IRUGO" by "0444" throughout. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> [sboyd@codeaurora.org: Squash the octal change in too] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-11clk: Show symbolic clock flags in debugfsGeert Uytterhoeven1-2/+55
Currently the virtual "clk_flags" file in debugfs shows the numeric value of the top-level framework flags for the specified clock. Hence the user must manually interpret these values. Moreover, on big-endian 64-bit systems, the wrong half of the value is shown, due to the cast from "unsigned long *" to "u32 *". Fix both issues by showing the symbolic flag names instead. Any non-standard flags are shown as a hex number. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-05clk: renesas: r8a7796: Add FDP clockABE Hiroshige1-0/+1
This patch adds FDP1-0 clock to the R8A7796 SoC. Signed-off-by: ABE Hiroshige <hiroshige.abe.zc@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: s/fdp0/fdp1-0/] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2018-01-05clk: Move __clk_{get,put}() into private clk.h APIStephen Boyd1-0/+4
We can move these APIs into the private header file now that we don't have any users of the __clk_get() and __clk_put() APIs outside of clkdev.c and clk.c. Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-05clk: sunxi: Use CLK_IS_CRITICAL flag for critical clksStephen Boyd6-47/+44
We'd like to privatize __clk_get(), but the sunxi clk driver is calling this function to keep a reference held on the clk and call clk_prepare_enable() on it. We support this design in the clk core now with the CLK_IS_CRITICAL flag, so let's just use that instead. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-20 02:47:35 +0300