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2020-03-21clk: mmp2: Add support for PLL clock sourcesLubomir Rintel4-1/+195
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are constant, but in fact they are configurable. Add logic for obtaining the actual clock rates on MMP2 as well as MMP3. There is no documentation for either SoC, but the "systemsetting" drivers from Marvell GPL code dump provide some clue as far as MPMU registers on MMP2 [1] and MMP3 [2] go. [1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c [2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c A separate commit will adjust the clk-of-mmp2 driver. Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC XO-1.75 laptop. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-5-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: Constify some stringsLubomir Rintel3-9/+10
All the parent clock names for the muxes are constant. Add const. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-3-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: Remove a unused prototypeLubomir Rintel1-3/+0
There is no mmp_clk_register_pll2() routine. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-2-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: at91: add at91rm9200 pmc driverAlexandre Belloni2-0/+200
Add a driver for the PMC clocks of the at91rm9200. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/20200214145934.53648-1-alexandre.belloni@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: versatile: Add device tree probing for IM-PD1 clocksLinus Walleij2-0/+80
As we want to move these clocks over to probe from the device tree we add a device tree probing path. The old platform data path will be deleted once we have the device tree overall code in place. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lkml.kernel.org/r/20200219103326.81120-3-linus.walleij@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: versatile: Export icst_clk_setup()Linus Walleij2-18/+28
Export this clock setup method so we can register the IM-PD1 clocks with common code in the next step. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lkml.kernel.org/r/20200219103326.81120-2-linus.walleij@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: Fix trivia typo in comment exlusive => exclusiveAndy Shevchenko1-1/+1
Fix trivia typo in comment exlusive => exclusive. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lkml.kernel.org/r/20200310135507.87959-1-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil1-1/+1
When requesting a rate superior to the parent's rate, it would return -EINVAL instead of simply returning the parent's rate like it should. Fixes: 4f89e4b8f121 ("clk: ingenic: Add driver for the TCU clocks") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200213161952.37460-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil1-1/+3
Exit jz4770_cgu_init() if the 'cgu' pointer we get is NULL, since the pointer is passed as argument to functions later on. Fixes: 7a01c19007ad ("clk: Add Ingenic jz4770 CGU driver") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lkml.kernel.org/r/20200213161952.37460-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: keystone: Add new driver to handle syscon based clocksVignesh Raghavendra3-0/+181
On TI's AM654/J721e SoCs, certain clocks can be gated/ungated by setting a single bit in SoC's System Control Module registers. Sometime more than one clock control can be in the same register. Add a driver to support such clocks using syscon framework. Driver currently supports controlling EHRPWM's TimeBase clock(TBCLK) for AM654 SoC. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lkml.kernel.org/r/20200227053529.16479-3-vigneshr@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)1-5/+50
Add "jz4780_core1_enable()" for enable the second core of JZ4780, prepare for later commits. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> Tested-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)1-0/+8
X1000 has a different TCU, since X1000 OST has been independent of TCU. This patch is add TCU support of X1000, and prepare for later OST driver. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lkml.kernel.org/r/1584457893-40418-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150Wesley Cheng1-0/+52
This adds the USB3 PIPE clock and GDSC structures, so that the USB driver can vote for these resources to be enabled/disabled when required. Both are needed for SS and HS USB paths to operate properly. The GDSC will allow the USB system to be brought out of reset, while the PIPE clock is needed for data transactions between the PHY and controller. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lkml.kernel.org/r/1584478412-7798-2-git-send-email-wcheng@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21ipq806x: gcc: Added the enable regs and mask for PRNGAbhishek Sahu1-0/+2
Kernel got hanged while reading from /dev/hwrng at the time of PRNG clock enable Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: qcom: Add modem clock controller driver for SC7180Taniya Das3-0/+153
Add support for the modem clock controller found on SC7180 based devices. This would allow modem drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1584596131-22741-4-git-send-email-tdas@codeaurora.org Tested-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: qcom: gcc: Add support for modem clocks in GCCTaniya Das1-1/+71
Add the required modem clocks in global clock controller which are required to bring the modem out of reset. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1584596131-22741-3-git-send-email-tdas@codeaurora.org Tested-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-17clk: ti: Fix dm814x clkctrl for ethernetTony Lindgren1-1/+6
We are missing alwon ethernet clock for dm814x and this prevents us from probing the CPSW with device tree only data. Looks like Ethernet currently only works if it has been enabled in the bootloader. Looks like relying on the bootloader clocks is not an issue with the mainline kernel currently, but it will be an issue when configuring CPSW Ethernet to probe with device tree data only as we will be managing the clocks. Fixes: 26ca2e973844 ("clk: ti: dm814: add clkctrl clock data") Cc: linux-clk@vger.kernel.org Cc: Graeme Smecher <gsmecher@threespeedlogic.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-03-16clk: ti: am43xx: Fix clock parent for RTC clockTony Lindgren1-1/+1
Currently enabling clkctrl clock on am4 can fail for RTC as the clock parent is wrong for RTC. Fixes: 76a1049b84dd ("clk: ti: am43xx: add new clkctrl data for am43xx") Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lkml.kernel.org/r/20200221171030.39326-1-tony@atomide.com Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-16Merge tag 'imx-clk-fixes-5.6-2' of ↵Stephen Boyd1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes Pull a few more i.MX clk fixes for 5.6: - A couple of fixes on i.MX8MP clock driver to correct HDMI_AXI and ENET_QOS_ROOT parent clock * tag 'imx-clk-fixes-5.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx8mp: Correct the enet_qos parent clock clk: imx8mp: Correct IMX8MP_CLK_HDMI_AXI clock parent
2020-03-16clk: imx: clk-gate2: Pass the device to the register functionAbel Vesa1-1/+1
The device needs to be passed on to the clk_hw_register. Fixes: 1f9aec9662566189 ("clk: imx: clk-gate2: Switch to clk_hw based API") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-16clk: imx7d: Add PXP clockLaurent Pinchart1-0/+1
The PXP has a single CCGR clock gate, gating both the IPG_CLK_ROOT and the MAIN_AXI_CLK_ROOT. Add a single clock to cover both. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-16clk: imx8mp: Correct the enet_qos parent clockFugang Duan1-1/+1
enet_qos is for eqos tsn AXI bus clock whose clock source is from ccm_enet_axi_clk_root, and controlled by CCM_CCGR59(offset 0x43b0) and CCM_CCGR64(offset 0x4400), so correct enet_qos root clock's parent clock to sim_enet. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-16clk: imx8mp: Correct IMX8MP_CLK_HDMI_AXI clock parentAnson Huang1-1/+1
IMX8MP_CLK_HDMI_AXI should be from imx8mp_media_axi_sels instead of imx8mp_media_apb_sels, fix it. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-13clk: qcom: clk-rpm: add missing rpm clk for ipq806xAnsuel Smith1-0/+35
Add missing definition of rpm clk for ipq806x soc Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Acked-by: John Crispin <john@phrozen.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-12clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni5-15/+10
Current clock driver enables PLLA, cdev1 on Tegra20 and extern1 on Tegra30 and above as a part of clocks init and there is no need to have these audio clocks enabled by the clock driver. extern1 is used as parent for clk_out_1 and clk_out_1 is dedicated for audio mclk on Tegra30 and above Tegra platforms and these clocks are taken care by ASoC driver. So, this patch removes audio related clocks configuration from clock init of Tegra20 and above. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni9-201/+19
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2, clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct PMC register access during clk_ops and these PMC register read and write access will not happen when PMC is in secure mode. Any direct PMC register access from non-secure world will not go through. All the PMC clocks are moved to Tegra PMC driver with PMC as a clock provider. This patch removes tegra_pmc_clk_init along with corresponding clk ids from Tegra clock driver. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni6-45/+0
Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible parents of PMC clocks for Tegra30 through Tegra210. Tegra PMC clock parents are changed to use OSC_DIV clocks. So, this patch removes CLK_M_DIV fixed clocks Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni1-6/+6
Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3 supported parents are osc, osc_div2, osc_div4 and extern clock. Clock driver is using incorrect parents clk_m, clk_m_div2, clk_m_div4 for PMC clocks. This patch fixes this. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni6-0/+14
OSC is one of the parent for Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3. This patch adds Tegra OSC to clock lookup. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni6-0/+34
Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks from the OSC pads. This patch adds support for these clocks. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-11clk: imx8mq: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11clk: imx8mp: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11clk: imx8mm: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11clk: imx8mn: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: imx: pllv4: use prepare/unpreparePeng Fan1-6/+6
It is not good to use enable/disable for PLLv4 which needs time to lock, because enable/disable is expected to be able run in interrupt context. So use prepare/unprepare. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: imx: pfdv2: determine best parent ratePeng Fan1-17/+33
pfdv2 is only used in i.MX7ULP. To get best pfd output, the i.MX7ULP Datasheet defines two best PLL rate and pfd frac. Per Datasheel All PLLs on i.MX 7ULP either have VCO base frequency of 480 MHz or 528 MHz. So when determine best rate, we also determine best parent rate which could match the requirement. For some reason the current parent might not be 480MHz or 528MHz, so we still take current parent rate as a choice. And we also enable flag CLK_SET_RATE_PARENT to let parent rate to be configured. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: imx: pfdv2: switch to use determine_ratePeng Fan1-6/+9
Per clk_ops, compared with round_rate, determine_rate could optionally support the parent clock that should be used to provide the clock rate. In this patch, the parent clock is just parent->rate as round_rate. The following patch will calculate the best parent clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: imx: Fix division by zero warning on pfdv2Anson Huang1-0/+6
Fix below division by zero warning: [ 3.176443] Division by zero in kernel. [ 3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124 [ 3.191817] Hardware name: Freescale i.MX7ULP (Device Tree) [ 3.197821] Workqueue: events dbs_work_handler [ 3.202849] [<c01127d8>] (unwind_backtrace) from [<c010cd80>] (show_stack+0x10/0x14) [ 3.211058] [<c010cd80>] (show_stack) from [<c0c77e68>] (dump_stack+0xd8/0x110) [ 3.218820] [<c0c77e68>] (dump_stack) from [<c0c753c0>] (Ldiv0_64+0x8/0x18) [ 3.226263] [<c0c753c0>] (Ldiv0_64) from [<c05984b4>] (clk_pfdv2_set_rate+0x54/0xac) [ 3.234487] [<c05984b4>] (clk_pfdv2_set_rate) from [<c059192c>] (clk_change_rate+0x1a4/0x698) [ 3.243468] [<c059192c>] (clk_change_rate) from [<c0591a08>] (clk_change_rate+0x280/0x698) [ 3.252180] [<c0591a08>] (clk_change_rate) from [<c0591fc0>] (clk_core_set_rate_nolock+0x1a0/0x278) [ 3.261679] [<c0591fc0>] (clk_core_set_rate_nolock) from [<c05920c8>] (clk_set_rate+0x30/0x64) [ 3.270743] [<c05920c8>] (clk_set_rate) from [<c089cb88>] (imx7ulp_set_target+0x184/0x2a4) [ 3.279501] [<c089cb88>] (imx7ulp_set_target) from [<c0896358>] (__cpufreq_driver_target+0x188/0x514) [ 3.289196] [<c0896358>] (__cpufreq_driver_target) from [<c0899b0c>] (od_dbs_update+0x130/0x15c) [ 3.298438] [<c0899b0c>] (od_dbs_update) from [<c089a5d0>] (dbs_work_handler+0x2c/0x5c) [ 3.306914] [<c089a5d0>] (dbs_work_handler) from [<c0156858>] (process_one_work+0x2ac/0x704) [ 3.315826] [<c0156858>] (process_one_work) from [<c0156cdc>] (worker_thread+0x2c/0x574) [ 3.324404] [<c0156cdc>] (worker_thread) from [<c015cfe8>] (kthread+0x134/0x148) [ 3.332278] [<c015cfe8>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20) [ 3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8) [ 3.345314] 5fa0: 00000000 00000000 00000000 00000000 [ 3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: qcom: gcc: Add global clock controller driver for SM8250Taniya Das3-0/+3698
Add the clocks supported in global clock controller, which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-6-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-10clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLsTaniya Das2-0/+205
Add programming sequence support for managing the Lucid PLLs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-4-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-10clk: qcom: clk-alpha-pll: Refactor trion PLLTaniya Das1-27/+6
Remove duplicate function for calculating the round rate of PLL and also update the trion pll ops to use the common function. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-3-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-10clk: qcom: clk-alpha-pll: Use common names for definesTaniya Das1-23/+17
The PLL run and standby modes are similar across the PLLs, thus rename them to common names and update the use of these. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-2-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-10clk: qcom: smd: Add support for MSM8976 rpm clocksAngeloGioacchino Del Regno1-0/+50
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8976, MSM8956 (and APQ variants) for clients to vote on. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Link: https://lkml.kernel.org/r/20191031112951.35850-2-kholk11@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-10clk: qcom: clk-rpmh: Wait for completion when enabling clocksMike Tipton1-2/+13
The current implementation always uses rpmh_write_async, which doesn't wait for completion. That's fine for disable requests since there's no immediate need for the clocks and they can be disabled in the background. However, for enable requests we need to ensure the clocks are actually enabled before returning to the client. Otherwise, clients can end up accessing their HW before the necessary clocks are enabled, which can lead to bus errors. Use the synchronous version of this API (rpmh_write) for enable requests in the active set to ensure completion. Completion isn't required for sleep/wake sets, since they don't take effect until after we enter sleep. All rpmh requests are automatically flushed prior to entering sleep. Fixes: 9c7e47025a6b ("clk: qcom: clk-rpmh: Add QCOM RPMh clock driver") Signed-off-by: Mike Tipton <mdtipton@codeaurora.org> Link: https://lkml.kernel.org/r/20200215021232.1149-1-mdtipton@codeaurora.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: Reorg code a bit for readability, rename to 'wait' to make local variable not conflict with completion.h mechanism] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-09clk: renesas: rcar-usb2-clock-sel: Add reset_controlYoshihiro Shimoda2-1/+15
This hardware needs to deassert resets of both host and peripheral. So, this patch adds reset control. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-09clk: renesas: rcar-usb2-clock-sel: Add multiple clocks managementYoshihiro Shimoda1-2/+25
This hardware needs to enable clocks of both host and peripheral. So, this patch adds multiple clocks management. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1583304137-28482-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-06clk: rockchip: fix mmc get phaseJerome Brunet1-2/+2
If the mmc clock has no rate, it can be assumed to be constant. In such case, there is no measurable phase shift. Just return 0 in this case instead of returning an error. Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration") Tested-by: Markus Reichl <m.reichl@fivetechno.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-02-28clk: Fix phase init checkMaxime Ripard1-2/+4
Commit 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration") introduced a check on error values at the time the clock is registered to bail out when such an error occurs. However, it doesn't check whether the returned value is positive which will happen if the driver returns a non-zero phase. Since a phase is usually a non-zero positive number this ends up returning something that isn't 0 to the caller of __clk_core_init(), making most clks fail to register if they implement a phase clk op and return anything besides 0 for the phase. Fix this by returning the error if phase is less than zero or just return zero if the phase is a positive number. Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lkml.kernel.org/r/20200225134248.919889-1-maxime@cerno.tech Reported-by: "kernelci.org bot" <bot@kernelci.org> [sboyd@kernel.org: Reword commit text to provide clarity] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-02-24clk: imx: clk-sscg-pll: Drop unnecessary initializationAnson Huang1-7/+7
No need to initialize 'ret' in many functions, as it will get the return value from function call, so remove the initializtion of 'ret'. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-24clk: imx: pll14xx: Return error if pll type is invalidAnson Huang1-0/+2
When pll type is invalid, ONLY output error message is NOT enough, should return error immediately. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 22:51:54 +0300