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2020-04-28firmware: xilinx: Use APIs instead of IOCTLsRajan Vaja1-10/+4
Remove IOCTL API and use individual APIs for better readability. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-12-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for clock set/get parentRajan Vaja1-4/+2
Use direct function call instead of eemi ops for clock set/get parent. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-11-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for clock_getdividerRajan Vaja2-5/+3
Use direct function call instead of using eemi ops for clock_getdivider. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-9-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for clock_setdividerRajan Vaja2-4/+3
Use direct function call instead of using eemi ops for clock_setdivider. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-8-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for clock_getstateRajan Vaja2-4/+2
Use direct function call instead of eemi ops for clock_getstate. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-7-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for clock_disableRajan Vaja2-5/+2
Use direct function call for clock_disable instead using of eemi ops. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-6-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for clock_enableRajan Vaja2-3/+2
Use direct function call for clock_enable instead of eemi ops. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-5-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for query_dataRajan Vaja2-13/+7
Use direct function call for query_data instead of using eemi ops. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-4-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-22clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue1-4/+4
During the process of debugging a processor derived from the msm8916 which we found the new processor was not starting one of its PLLs. After tracing the addresses and writes that downstream was doing and comparing to upstream it became obvious that we were writing to a different register location than downstream when trying to configure the PLL. This error is also present in upstream msm8916. As an example clk-pll.c::clk_pll_recalc_rate wants to write to pll->config_reg updating the bit-field POST_DIV_RATIO. That bit-field is defined in PLL_USER_CTL not in PLL_CONFIG_CTL. Taking the BIMC PLL as an example lm80-p0436-13_c_qc_snapdragon_410_processor_hrd.pdf 0x01823010 GCC_BIMC_PLL_USER_CTL 0x01823014 GCC_BIMC_PLL_CONFIG_CTL This pattern is repeated for gpll0, gpll1, gpll2 and bimc_pll. This error is likely not apparent since the bootloader will already have initialized these PLLs. This patch corrects the location of config_reg from PLL_CONFIG_CTL to PLL_USER_CTL for all relevant PLLs on msm8916. Fixes commit 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Cc: Georgi Djakov <georgi.djakov@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lkml.kernel.org/r/20200329124116.4185447-1-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-04-20clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock waitAnson Huang1-11/+5
Use readl_relaxed_poll_timeout() for PLL lock wait which can simplify the code a lot. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-20clk: imx: clk-sscg-pll: Remove unnecessary blank linesAnson Huang1-10/+0
Remove many unnecessary blank lines for cleanup. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-16clk: meson: g12a: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl1-8/+22
The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also propagate set_rate requests from the gate to the divider and from the divider to the the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Don't propagate rate changes to the mux parents because we don't want to change the MPLL clocks (these are reserved for audio). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200414195031.224021-3-martin.blumenstingl@googlemail.com
2020-04-16clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl1-18/+22
The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also propagate set_rate requests from the gate to the divider and from the divider to the the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Don't propagate rate changes to the mux parents because we don't want to change the MPLL clocks (these are reserved for audio). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200414195031.224021-2-martin.blumenstingl@googlemail.com
2020-04-14clk: imx: drop the dependency on ARM64 for i.MX8MPeng Fan1-4/+4
Moving to support aarch32 mode on aarch64 hardware, need to drop the dependency on ARM64 to make the driver could be selected for ARM32. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-14clk: imx7ulp: make it easy to change ARM core clkPeng Fan1-2/+4
ARM clk could only source from divcore or hsrun_divcore. Follow what we already used on i.MX7D and i.MX8M SoCs, use imx_clk_hw_cpu API. When ARM core is running normaly, whether divcore or hwrun_divcore will finally source from SPLL_PFD0. However SPLL_PFD0 is marked with CLK_SET_GATE, so we need to disable SPLL_PFD0, when configure the rate. So add CORE and HSRUN_CORE virtual clk to make it easy to configure the clk using imx_clk_hw_cpu API. Since CORE and HSRUN_CORE already marked with CLK_IS_CRITICAL, no need to set ARM as CLK_IS_CRITICAL. And when set the rate of ARM clk, prograting it the parent with CLK_SET_RATE_PARENT will finally set the SPLL_PFD0 clk. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-14clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl1-3/+3
The HDMI TX controller requires the hdmi_sys clock to be enabled. Allow changing the whole clock tree now that we know that one of our drivers requires this. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200330234535.3327513-3-martin.blumenstingl@googlemail.com
2020-04-14clk: meson8b: export the HDMI system clockMartin Blumenstingl1-1/+0
Export the HDMI system clock (used by the HDMI transmitter) so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200330234535.3327513-2-martin.blumenstingl@googlemail.com
2020-04-14clk: renesas: r9a06g032: Fix some typo in commentsChristophe JAILLET1-3/+3
This file seems to be for R9A06G032 only. So replace reference to R9A09G032 by R9A06G032 to avoid confusion. AFAIK, R9A09G032 does'nt exist. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20200413041709.3630-1-christophe.jaillet@wanadoo.fr Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-14clk: sunxi: Fix incorrect usage of round_down()Rikard Falkeborn1-1/+1
round_down() can only round to powers of 2. If round_down() is asked to round to something that is not a power of 2, incorrect results are produced. The incorrect results can be both too large and too small. Instead, use rounddown() which can round to any number. Fixes: 6a721db180a2 ("clk: sunxi: Add A31 clocks support") Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-04-13clk: sprd: don't gate uart console clockChunyan Zhang1-1/+2
Don't gate uart1_eb which provides console clock, gating that clock would make serial stop working if serial driver didn't enable that explicitly. Fixes: 0e4b8a2349f3 ("clk: sprd: add clocks support for SC9863A") Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200408020234.31764-1-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-04-13clk: mmp2: fix link error without mmp2Arnd Bergmann3-39/+32
The newly added function is only built into the kernel if mmp2 is enabled, causing a link error otherwise. arm-linux-gnueabi-ld: drivers/clk/mmp/clk.o: in function `mmp_register_pll_clks': clk.c:(.text+0x6dc): undefined reference to `mmp_clk_register_pll' Move it to a different file to get it to link. Fixes: 5d34d0b32d6c ("clk: mmp2: Add support for PLL clock sources") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/20200408160518.2798571-1-arnd@arndb.de Reported-by: Guenter Roeck <linux@roeck-us.net> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-04-13clk: asm9260: fix __clk_hw_register_fixed_rate_with_accuracy typoArnd Bergmann1-1/+1
The __clk_hw_register_fixed_rate_with_accuracy() function (with two '_') does not exist, and apparently never did: drivers/clk/clk-asm9260.c: In function 'asm9260_acc_init': drivers/clk/clk-asm9260.c:279:7: error: implicit declaration of function '__clk_hw_register_fixed_rate_with_accuracy'; did you mean 'clk_hw_register_fixed_rate_with_accuracy'? [-Werror=implicit-function-declaration] 279 | hw = __clk_hw_register_fixed_rate_with_accuracy(NULL, NULL, pll_clk, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | clk_hw_register_fixed_rate_with_accuracy drivers/clk/clk-asm9260.c:279:5: error: assignment to 'struct clk_hw *' from 'int' makes pointer from integer without a cast [-Werror=int-conversion] 279 | hw = __clk_hw_register_fixed_rate_with_accuracy(NULL, NULL, pll_clk, | ^ From what I can tell, __clk_hw_register_fixed_rate() is the correct API here, so use that instead. Fixes: 728e3096741a ("clk: asm9260: Use parent accuracy in fixed rate clk") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/20200408155402.2138446-1-arnd@arndb.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-04-13clk: imx: imx6ul: change flexcan clock to support CiA bitratesWaibel Georg1-1/+1
Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock frequency from 30MHz to 40MHz which allows to support all bitrates recommended by CiA. The patch sets CAN_CLK_SEL to 80MHz by changing its clock parent from CLK_PLL3_60M to CLK_PLL3_80M. The post-divider CAN_CLK_PODF is set to /2 by default which makes 40MHz CAN_CLK_ROOT from its parent CAN_CLK_SEL. Background: CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50, 125, 250, 500, 800 and 1000kbit/s. With the flexcan serial clock at 30MHz (original value) setting some common bitrates ("ip link set canX type can bitrate <bitrate>") gives the following results: requested value / actually set value 5000: bitrate 5000 sample-point 0.708 10000: bitrate 10000 sample-point 0.866 20000: bitrate 20000 sample-point 0.866 40000: bitrate 40000 sample-point 0.866 50000: bitrate 50000 sample-point 0.866 80000: bitrate 80000 sample-point 0.866 100000: bitrate 100000 sample-point 0.866 125000: bitrate 125000 sample-point 0.875 250000: bitrate 250000 sample-point 0.866 400000: bitrate 400000 sample-point 0.866 500000: bitrate 500000 sample-point 0.866 666666: bitrate 666666 sample-point 0.800 800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3% 1000000: bitrate 1000000 sample-point 0.733 With the flexcan serial clock at 40MHz (new value) we get this: 5000: no more possible 10000: bitrate 10000 sample-point 0.875 20000: bitrate 20000 sample-point 0.875 40000: bitrate 40000 sample-point 0.850 50000: bitrate 50000 sample-point 0.875 80000: bitrate 80000 sample-point 0.850 100000: bitrate 100000 sample-point 0.875 125000: bitrate 125000 sample-point 0.875 250000: bitrate 250000 sample-point 0.875 400000: bitrate 400000 sample-point 0.850 500000: bitrate 500000 sample-point 0.875 666666: bitrate 666666 sample-point 0.800 800000: bitrate 800000 sample-point 0.800 1000000: bitrate 1000000 sample-point 0.750 A drawback of the modification is that 5kbit/s is no more supported. Setting the flexcan serial clock to 60MHz or 80MHz would produce similar results but with losing even more bitrates at the lower end. Changing the flexcan serial clock to 40MHz might apply for other SoCs using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't have such hardware to test I did not add this to the patch. Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-13clk / soc: mediatek: Move mt8173 MMSYS to platform driverMatthias Brugger4-104/+154
There is no strong reason for this to use CLK_OF_DECLARE instead of being a platform driver. Plus, MMSYS provides clocks but also a shared register space for the mediatek-drm and the mediatek-mdp driver. So move the MMSYS clocks to a new platform driver and also create a new MMSYS platform driver in drivers/soc/mediatek that instantiates the clock driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocksJustin Swartz1-13/+4
The following changes prevent the unrecoverable freezes and rcu_sched stall warnings experienced in each of my attempts to take advantage of lima. Replace the COMPOSITE_NOGATE definition of aclk_gpu_pre with a COMPOSITE that retains the selection of HDMIPHY as the PLL source, but instead makes uses of the aclk_gpu PLL source gate and parent names defined by mux_pll_src_4plls_p rather than mux_aclk_gpu_pre_p. Remove the now unused mux_aclk_gpu_pre_p and the four named but also unused definitions (cpll_gpu, gpll_gpu, hdmiphy_gpu and usb480m_gpu) of the aclk_gpu PLL source gate. Use the correct gate offset for aclk_gpu and aclk_gpu_noc. Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228") Cc: stable@vger.kernel.org Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> [double-checked against SoC manual and added fixes tag] Link: https://lore.kernel.org/r/20200114162503.7548-1-justin.swartz@risingedge.co.za Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-04-05Merge tag 'clk-for-linus' of ↵Linus Torvalds95-796/+8934
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's not much to see in the core framework this time around. Instead the majority of the diff is the normal collection of driver additions for new SoCs and non-critical clk data fixes and updates. The framework must be middle aged. The two biggest directories in the diffstat show that the Qualcomm and Unisoc support added a handful of big drivers for new SoCs but that's not really the whole story because those new drivers tend to add large numbers of lines of clk data. There's a handful of AT91 clk drivers added this time around too and a bunch of improvements to drivers like the i.MX driver. All around lots of updates and fixes in various clk drivers which is good to see. The core framework has only one real major change which has been baking in next for the past couple months. It fixes the framework so that it stops caching a clk's phase when the phase clk_op returns an error. Before this change we would consider some negative errno as a phase and that just doesn't make sense. Core: - Don't show clk phase when it is invalid New Drivers: - Add support for Unisoc SC9863A clks - Qualcomm SM8250 RPMh and MSM8976 RPM clks - Qualcomm SM8250 Global Clock Controller (GCC) support - Qualcomm SC7180 Modem Clock Controller (MSS CC) support - EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs Updates: - GPU GX GDSC support on Qualcomm sc7180 - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers - A series from Anson to convert i.MX8 clock bindings to json-schema - Update i.MX pll14xx driver to include new frequency entries for pll1443x table, and return error for invalid PLL type - Add missing of_node_put() call for a number of i.MX clock drivers - Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already have the flag on its child cpu clock - Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL via CORE_SEL slice, and source from A53 CCM clk root when we need to change ARM PLL frequency. Thus, we can support core running above 1GHz safely - Update i.MX pfdv2 driver to check zero rate and use determine_rate for getting the best rate - Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d - Remove PMC clks from Tegra clk driver - Improved clock/reset handling for the Renesas R-Car USB2 Clock Selector - Conversion to json-schema of the Renesas CPG/MSSR DT bindings - Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3 - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and M3-N - Update Amlogic audio clock gate hierarchy for meson8 and gxbb - Update Amlogic g12a spicc clock sources - Support for Ingenic X1000 TCU clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (146 commits) clk: sprd: fix to get a correct ibias of pll dt-bindings: imx8mm-clock: Fix the file path dt-bindings: imx8mq-clock: Fix the file path clk: qcom: rpmh: Drop unnecessary semicolons clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd() clk: tegra: Use NULL for pointer initialization clk: sprd: add clocks support for SC9863A clk: sprd: support to get regmap from parent node clk: sprd: Add macros for referencing parents without strings clk: sprd: Add dt-bindings include file for SC9863A dt-bindings: clk: sprd: add bindings for sc9863a clock controller dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific clk: sprd: add gate for pll clocks MAINTAINERS: dt: update reference for arm-integrator.txt clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks clk: mmp2: Add clock for fifth SD HCI on MMP3 dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 clk: mmp2: Add clocks for the thermal sensors dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors clk: mmp2: add the GPU clocks ...
2020-04-04Merge tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2-1/+7
Pull ARM devicetree updates from Arnd Bergmann: "Most of the commits are for additional hardware support and minor fixes for existing machines for all the usual platforms: qcom, amlogic, at91, gemini, mediatek, ti, socfpga, i.mx, layerscape, uniphier, rockchip, exynos, ux500, mvebu, tegra, stm32, renesas, sunxi, broadcom, omap, and versatile. The conversion of binding files to machine-readable yaml format continues, along with fixes found during the validation. Andre Przywara takes over maintainership for the old Calxeda Highbank platform and provides a number of updates. The OMAP2+ platforms see a continued move from platform data into dts files, for many devices that relied on a mix of auxiliary data in addition to the DT description A moderate number of new SoCs and machines are added, here is a full list: - Two new Qualcomm SoCs with their evaluation boards: Snapdragon 865 (SM8250) is the current high-end phone chip, and IPQ6018 is a new WiFi-6 router chip. - Mediatek MT8516 application processor SoC for voice assistants, along with the "pumpkin" development board - NXP i.MX8M Plus SoC, a variant of the popular i.MX8M, along with an evaluation board. - Kontron "sl28" board family based on NXP LS1028A - Eleven variations of the new i.MX6 TechNexion Pico board, combining the "dwarf", "hobbit", "nymph" and "pi" baseboards with i.MX6/i.MX7 SoM carriers - Three additional variants of the Toradex Colibri board family, all based on versions of the NXP i.MX7. - The Pinebook Pro laptop based on Rockchip RK3399 - Samsung S7710 Galaxy Xcover 2, a 2013 vintage Android phone based on the ST-Ericsson u8500 platform - DH Electronics DHCOM SoM and PDK2 rev. 400 carrier based on STMicroelectronics stm32mp157 - Renesas M3ULCB starter kit for R-Car M3-W+ - Hoperun HiHope development board with Renesas RZ/G2M - Pine64 PineTab tablet and PinePhone phone, both based on Allwinner A64 - Linutronix Testbox v2 for the Lamobo R1 router, based on Allwinner A20 - PocketBook Touch Lux 3 ebook reader, based on Allwinner A13" * tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (520 commits) ARM: dts: ux500: Fix missing node renames arm64: dts: Revert "specify console via command line" MAINTAINERS: Update Calxeda Highbank maintainership arm: dts: calxeda: Group port-phys and sgpio-gpio items arm: dts: calxeda: Fix interrupt grouping arm: dts: calxeda: Provide UART clock arm: dts: calxeda: Basic DT file fixes arm64: dts: specify console via command line ARM: dts: at91: sama5d27_wlsom1_ek: add USB device node ARM: dts: gemini: Add thermal zone to DIR-685 ARM: dts: gemini: Rename IDE nodes ARM: socfpga: arria10: Add ptp_ref clock to ethernet nodes arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0 arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node arm64: dts: khadas-vim3: add SPIFC controller node ...
2020-04-04Merge branches 'clk-unisoc', 'clk-tegra', 'clk-qcom' and 'clk-imx' into clk-nextStephen Boyd50-508/+6697
- Add support for Unisoc SC9863A clks - GPU GX GDSC support on Qualcomm sc7180 - Qualcomm SM8250 RPMh and MSM8976 RPM clks - Qualcomm SM8250 Global Clock Controller (GCC) support - Qualcomm SC7180 Modem Clock Controller (MSS CC) support * clk-unisoc: clk: sprd: fix to get a correct ibias of pll clk: sprd: add clocks support for SC9863A clk: sprd: support to get regmap from parent node clk: sprd: Add macros for referencing parents without strings clk: sprd: Add dt-bindings include file for SC9863A dt-bindings: clk: sprd: add bindings for sc9863a clock controller dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific clk: sprd: add gate for pll clocks * clk-tegra: clk: tegra: Use NULL for pointer initialization clk: tegra: Remove audio clocks configuration from clock driver clk: tegra: Remove tegra_pmc_clk_init along with clk ids clk: tegra: Remove CLK_M_DIV fixed clocks clk: tegra: Fix Tegra PMC clock out parents clk: tegra: Add Tegra OSC to clock lookup clk: tegra: Add support for OSC_DIV fixed clocks dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: clock: tegra: Add IDs for OSC clocks * clk-qcom: (21 commits) clk: qcom: rpmh: Drop unnecessary semicolons clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd() clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 ipq806x: gcc: Added the enable regs and mask for PRNG clk: qcom: Add modem clock controller driver for SC7180 clk: qcom: gcc: Add support for modem clocks in GCC dt-bindings: clock: Add YAML schemas for the QCOM MSS clock bindings clk: qcom: clk-rpm: add missing rpm clk for ipq806x clk: qcom: gcc: Add global clock controller driver for SM8250 dt-bindings: clock: Add SM8250 GCC clock bindings clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs clk: qcom: clk-alpha-pll: Refactor trion PLL clk: qcom: clk-alpha-pll: Use common names for defines dt-bindings: clock: rpmcc: Document msm8976 compatible clk: qcom: smd: Add support for MSM8976 rpm clocks clk: qcom: clk-rpmh: Wait for completion when enabling clocks clk: qcom: rpmh: Add support for RPMH clocks on SM8250 dt-bindings: clock: Add RPMHCC bindings for SM8250 clk: qcom: alpha-pll: Make error prints more informative clk: qcom: gpucc: Add support for GX GDSC for SC7180 ... * clk-imx: (43 commits) dt-bindings: imx8mm-clock: Fix the file path dt-bindings: imx8mq-clock: Fix the file path clk: imx: clk-gate2: Pass the device to the register function clk: imx7d: Add PXP clock clk: imx8mq: A53 core clock no need to be critical clk: imx8mp: A53 core clock no need to be critical clk: imx8mm: A53 core clock no need to be critical clk: imx8mn: A53 core clock no need to be critical clk: imx: pllv4: use prepare/unprepare clk: imx: pfdv2: determine best parent rate clk: imx: pfdv2: switch to use determine_rate clk: imx: Fix division by zero warning on pfdv2 clk: imx: clk-sscg-pll: Drop unnecessary initialization clk: imx: pll14xx: Return error if pll type is invalid clk: imx: imx8mp: fix a53 cpu clock clk: imx: imx8mn: fix a53 cpu clock clk: imx: imx8mm: fix a53 cpu clock clk: imx: imx8mq: fix a53 cpu clock clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock clk: imx8mn: Remove unused includes ...
2020-04-04Merge branches 'clk-ti', 'clk-ingenic', 'clk-typo', 'clk-at91', 'clk-mmp2' ↵Stephen Boyd23-55/+1598
and 'clk-arm-icst' into clk-next - EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers * clk-ti: clk: keystone: Add new driver to handle syscon based clocks dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK * clk-ingenic: clk: ingenic/TCU: Fix round_rate returning error clk: ingenic/jz4770: Exit with error if CGU init failed clk: JZ4780: Add function for enable the second core. clk: Ingenic: Add support for TCU of X1000. * clk-typo: clk: Fix trivia typo in comment exlusive => exclusive * clk-at91: clk: at91: add at91rm9200 pmc driver clk: at91: add at91sam9n12 pmc driver clk: at91: add sama5d3 pmc driver clk: at91: add at91sam9g45 pmc driver clk: at91: usb: introduce num_parents in driver's structure clk: at91: usb: use proper usbs_mask clk: at91: sam9x60: fix usb clock parents clk: at91: usb: continue if clk_hw_round_rate() return zero clk: at91: sam9x60: Don't use audio PLL * clk-mmp2: clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks clk: mmp2: Add clock for fifth SD HCI on MMP3 dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 clk: mmp2: Add clocks for the thermal sensors dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors clk: mmp2: add the GPU clocks dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks clk: mmp2: Add PLLs that are available on MMP3 dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs clk: mmp2: Check for MMP3 dt-bindings: clock: Add MMP3 compatible string clk: mmp2: Stop pretending PLL outputs are constant clk: mmp2: Add support for PLL clock sources dt-bindings: clock: Convert marvell,mmp2-clock to json-schema clk: mmp2: Constify some strings clk: mmp2: Remove a unused prototype * clk-arm-icst: MAINTAINERS: dt: update reference for arm-integrator.txt clk: versatile: Add device tree probing for IM-PD1 clocks clk: versatile: Export icst_clk_setup() dt-bindings: clock: Create YAML schema for ICST clocks
2020-04-04Merge branches 'clk-phase-errors', 'clk-amlogic', 'clk-renesas' and ↵Stephen Boyd16-118/+382
'clk-allwinner' into clk-next - Don't show clk phase when it is invalid * clk-phase-errors: clk: rockchip: fix mmc get phase clk: Fix phase init check clk: Bail out when calculating phase fails during clk registration clk: Move rate and accuracy recalc to mostly consumer APIs clk: Use 'parent' to shorten lines in __clk_core_init() clk: Don't cache errors from clk_ops::get_phase() * clk-amlogic: clk: meson: meson8b: set audio output clock hierarchy clk: meson: g12a: add support for the SPICC SCLK Source clocks dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: gxbb: set audio output clock hierarchy clk: meson: gxbb: add the gxl internal dac gate dt-bindings: clk: meson: add the gxl internal dac gate * clk-renesas: dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema clk: renesas: rcar-usb2-clock-sel: Add reset_control clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties clk: renesas: Remove use of ARCH_R8A7795 clk: renesas: r8a77965: Add RPC clocks clk: renesas: r8a7796: Add RPC clocks clk: renesas: r8a7795: Add RPC clocks clk: renesas: rcar-gen3: Add CCREE clocks * clk-allwinner: clk: sunxi-ng: sun8i-de2: Sort structures clk: sunxi-ng: sun8i-de2: Add R40 specific quirks clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 clk: sunxi-ng: sun8i-de2: Split out H5 definitions clk: sunxi-ng: a64: Export MBUS clock
2020-04-04Merge branches 'clk-samsung', 'clk-formatting', 'clk-si5341' and ↵Stephen Boyd7-111/+258
'clk-socfpga' into clk-next * clk-samsung: clk: samsung: Remove redundant check in samsung_cmu_register_one * clk-formatting: clk: Fix continuation of of_clk_detect_critical() * clk-si5341: clk, clk-si5341: Support multiple input ports * clk-socfpga: clk: socfpga: stratix10: simplify parameter passing clk: stratix10: use do_div() for 64-bit calculation
2020-04-04Merge tag 'arm-soc-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-54/+37
Pull ARM SoC updates from Arnd Bergmann: "The code changes are mostly for 32-bit platforms and include: - Lots of updates for the Nvidia Tegra platform, including cpuidle, pmc, and dt-binding changes - Microchip at91 power management updates for the recently added sam9x60 SoC - Treewide setup_irq deprecation by afzal mohammed - STMicroelectronics stm32 gains earlycon support - Renesas platforms with Cortex-A9 can now use the global timer - Some TI OMAP2+ platforms gain cpuidle support - Various cleanups for the i.MX6 and Orion platforms, as well as Kconfig files across all platforms" * tag 'arm-soc-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (75 commits) ARM: qcom: Add support for IPQ40xx ARM: mmp: replace setup_irq() by request_irq() ARM: cns3xxx: replace setup_irq() by request_irq() ARM: spear: replace setup_irq() by request_irq() ARM: ep93xx: Replace setup_irq() by request_irq() ARM: iop32x: replace setup_irq() by request_irq() arm: mach-dove: Mark dove_io_desc as __maybe_unused ARM: orion: replace setup_irq() by request_irq() ARM: debug: stm32: add UART early console support for STM32MP1 ARM: debug: stm32: add UART early console support for STM32H7 ARM: debug: stm32: add UART early console configuration for STM32F7 ARM: debug: stm32: add UART early console configuration for STM32F4 cpuidle: tegra: Disable CC6 state if LP2 unavailable cpuidle: tegra: Squash Tegra114 driver into the common driver cpuidle: tegra: Squash Tegra30 driver into the common driver cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle ARM: tegra: cpuidle: Remove unnecessary memory barrier ARM: tegra: cpuidle: Make abort_flag atomic ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2 ARM: tegra: Make outer_disable() open-coded ...
2020-04-03Merge branch 'arm/late' into arm/dtArnd Bergmann1-1/+6
Include originally "late" updates for OMAP and Qualcomm, now that it's not late any more. * arm/late: (122 commits) ARM: OMAP2+: Drop legacy platform data for ti81xx edma ARM: dts: Configure interconnect target module for ti816x edma ARM: dts: Configure interconnect target module for dm814x tptc3 ARM: dts: Configure interconnect target module for dm814x tptc2 ARM: dts: Configure interconnect target module for dm814x tptc1 ARM: dts: Configure interconnect target module for dm814x tptc0 ARM: dts: Configure interconnect target module for dm814x tpcc ARM: OMAP2+: Drop legacy platform data for dm814x cpsw ARM: dts: Configure interconnect target module for dm814x cpsw clk: ti: Fix dm814x clkctrl for ethernet arm64: dts: qcom: sdm845-mtp: Relocate remoteproc firmware arm64: dts: sdm845: add IPA information arm64: dts: qcom: db845c: add analog audio support arm64: dts: qcom: sdm845: add pinctrl nodes for quat i2s arm64: dts: qcom: c630: Enable audio support arm64: dts: qcom: sdm845: add apr nodes arm64: dts: qcom: sdm845: add slimbus nodes arm64: dts: qcom: sc7180: Update reg names for SDHC arm64: dts: qcom: qcs404: Enable CQE support for eMMC arm64: dts: msm8916: Add fastrpc node ...
2020-04-03clk: sprd: fix to get a correct ibias of pllChunyan Zhang1-3/+4
The current driver is getting a wrong ibias index of pll clocks from number 1. This patch fix that issue, then getting ibias index from 0. Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support") Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200330021640.14133-1-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-26clk: imx: Align imx sc clock parent msg structs to 4Leonard Crestez1-1/+1
The imx SC api strongly assumes that messages are composed out of 4-bytes words but some of our message structs have odd sizeofs. This produces many oopses with CONFIG_KASAN=y. Fix by marking with __aligned(4). Fixes: 666aed2d13ee ("clk: imx: scu: add set parent support") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Link: https://lkml.kernel.org/r/aad021e432b3062c142973d09b766656eec18fde.1582216144.git.leonard.crestez@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-26clk: imx: Align imx sc clock msg structs to 4Leonard Crestez1-3/+3
The imx SC api strongly assumes that messages are composed out of 4-bytes words but some of our message structs have odd sizeofs. This produces many oopses with CONFIG_KASAN=y. Fix by marking with __aligned(4). Fixes: fe37b4820417 ("clk: imx: add scu clock common part") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Link: https://lkml.kernel.org/r/10e97a04980d933b2cfecb6b124bf9046b6e4f16.1582216144.git.leonard.crestez@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-25clk: qcom: rpmh: Drop unnecessary semicolonsStephen Boyd1-4/+4
Some functions end in }; which is just bad style. Remove the extra semicolon. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200309221232.145630-3-sboyd@kernel.org
2020-03-25clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd()Stephen Boyd1-19/+14
This function has some duplication in unlocking a mutex and returns in a few different places. Let's use some if statements to consolidate code and make this a bit easier to read. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> CC: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200309221232.145630-2-sboyd@kernel.org
2020-03-25clk: tegra: Use NULL for pointer initializationStephen Boyd1-1/+1
This silences a sparse warning about using a plain integer instead of NULL for a pointer. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-25clk: sprd: add clocks support for SC9863AChunyan Zhang3-0/+1781
Add the list of clocks for the Unisoc SC9863A, along with clock initialization. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-8-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-25clk: sprd: support to get regmap from parent nodeChunyan Zhang1-1/+9
Some SC9863a clock nodes would be the child of a syscon node, clocks can use the regmap of syscon device directly for this kind of cases. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-7-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-25clk: sprd: Add macros for referencing parents without stringsChunyan Zhang5-55/+196
With the new clk parenting code, clk_init_data was expanded to include .parent_hws and .parent_data, for clk drivers to specify parents without name strings of clocks. Also some macros were added for using these two items to reference clock parents. Based on that to expand macros for sprd clocks: - SPRD_*_DATA, take an array of struct clk_parent_data * as its parents which should be a combination of .fw_name (devicetree clock-names), .hw (pointers to a local struct clk_hw). - SPRD_*_HW, take a local struct clk_hw pointer, instead of a string, as its parent. - SPRD_*_FW_NAME, take a string of clock-names decleared in the device tree as the clock parent. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-6-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-25clk: sprd: add gate for pll clocksXiaolong Zhang2-2/+36
Some sprd's gate clocks are used to the switch of pll, which need to wait a certain time for stable after being enabled. Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: Fix bit masks for LCDC I/O and pixel clocksLubomir Rintel1-2/+2
They were reversed because I read the datasheet upside down. Actually there is no datasheet, but I ended up understanding the comments in Open Firmware driver wrong. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-18-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: Add clock for fifth SD HCI on MMP3Lubomir Rintel1-0/+2
There's one extra SDHCI on MMP3, used by the internal SD card on OLPC XO-4. Add a clock for it. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-17-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: Add clocks for the thermal sensorsLubomir Rintel1-0/+16
The register definitions gotten from OLPC Open Firmware. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-15-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: add the GPU clocksLubomir Rintel1-0/+61
MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300. On both platforms there's an AXI bus interface clock that's common for all GPUs and each GPU core has a separate clock. Meaning of the relevant APMU_GPU bits were gotten from James Cameron's message and [1], the OLPC OS kernel source [2] and Marvell's MMP3 tree. [1] http://lists.laptop.org/pipermail/devel/2019-April/039053.html [2] http://dev.laptop.org/git/olpc-kernel/commit/arch/arm/mach-mmp/mmp2.c?h=arm-3.0-wip&id=8ce9f6122 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-13-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: Add PLLs that are available on MMP3Lubomir Rintel1-7/+27
There are more PLLs on MMP3 and are configured slightly differently. Tested on a MMP3-based Dell Wyse 3020 machine. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-10-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: Check for MMP3Lubomir Rintel1-0/+12
The MMP3's are similar enough to MMP2, but there are differencies, such are more clocks available on the newer model. We want to tell which platform are we on. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-8-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-21clk: mmp2: Stop pretending PLL outputs are constantLubomir Rintel1-2/+14
The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default, but also configurable. Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and set-pll2-988mhz Open Firmware words. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-6-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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