starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-08-31	clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate	Quanyang Wang	1	-16/+15
2022-01-25	clk: zynqmp: replace warn_once with pr_debug for failed clock ops	Michael Tretter	1	-16/+16
2021-06-29	clk: zynqmp: Use firmware specific common clock flags	Rajan Vaja	1	-1/+3
2021-06-26	clk: zynqmp: pll: Remove some dead code	Christophe JAILLET	1	-2/+0
2021-06-26	clk: zynqmp: fix compile testing without ZYNQMP_FIRMWARE	Michal Simek	1	-6/+16
2021-04-08	clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable	Quanyang Wang	1	-1/+11
2021-04-08	clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback	Quanyang Wang	1	-6/+6
2020-04-28	firmware: xilinx: Use APIs instead of IOCTLs	Rajan Vaja	1	-10/+4
2020-04-28	firmware: xilinx: Remove eemi ops for clock_getdivider	Rajan Vaja	1	-1/+1
2020-04-28	firmware: xilinx: Remove eemi ops for clock_setdivider	Rajan Vaja	1	-2/+2
2020-04-28	firmware: xilinx: Remove eemi ops for clock_getstate	Rajan Vaja	1	-2/+1
2020-04-28	firmware: xilinx: Remove eemi ops for clock_disable	Rajan Vaja	1	-2/+1
2020-04-28	firmware: xilinx: Remove eemi ops for clock_enable	Rajan Vaja	1	-2/+1
2020-01-24	clk: zynqmp: Warn user if clock user are more than allowed	Rajan Vaja	1	-2/+4
2018-10-09	drivers: clk: Add ZynqMP clock driver	Jolly Shah	1	-0/+335