starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2015-07-20	clk: zynq: Include clk.h	Stephen Boyd	1	-0/+1
2015-06-05	clk: make several parent names const	Uwe Kleine-König	1	-9/+16
2015-04-13	clk: don't use __initconst for non-const arrays	Uwe Kleine-König	1	-12/+12
2015-01-28	clk: zynq: Force CPU_2X clock to be ungated	Soren Brinkmann	1	-0/+1
2014-09-09	clk: zynq: Move const initdata into correct code section	Soren Brinkmann	1	-15/+14
2014-09-09	clk: zynq: Remove pointless return at end of void function	Soren Brinkmann	1	-1/+0
2014-09-09	clk: zynq: Remove unnecessary OOM message	Soren Brinkmann	1	-3/+1
2014-04-22	clk: zynq: Leave debug clocks in bootup state	Soren Brinkmann	1	-0/+12
2014-04-06	Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/...	Linus Torvalds	2	-11/+11
2014-03-17	ARM: zynq: Move of_clk_init from clock driver	Michal Simek	1	-2/+0
2014-02-26	clk: zynq: Use clk_readl/clk_writel helper function	Michal Simek	2	-11/+11
2014-02-10	ARM: zynq: Map I/O memory on clkc init	Michal Simek	1	-26/+63
2013-12-20	clk/zynq/clkc: Add 'fclk-enable' feature	Soren Brinkmann	1	-3/+15
2013-10-08	clk/zynq: Fix possible memory leak	Felipe Pena	1	-1/+15
2013-09-10	Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux	Linus Torvalds	2	-39/+62
2013-08-21	Merge tag 'zynq-clk-for-3.12' of git://git.xilinx.com/linux-xlnx into clk-next	Mike Turquette	1	-5/+14
2013-08-20	clk/zynq/pll: Use #defines for fbdiv min/max values	Soren Brinkmann	1	-4/+7
2013-08-20	clk/zynq/pll: Fix documentation for PLL register function	Soren Brinkmann	1	-1/+7
2013-08-19	clk: add CLK_SET_RATE_NO_REPARENT flag	James Hogan	1	-36/+50
2013-08-13	clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes	Soren Brinkmann	1	-4/+6
2013-08-13	clk/zynq/clkc: Add dedicated spinlock for the SWDT	Soren Brinkmann	1	-1/+2
2013-05-27	arm: zynq: Migrate platform to clock controller	Soren Brinkmann	1	-0/+3
2013-05-27	clk: zynq: Add clock controller driver	Soren Brinkmann	1	-0/+533
2013-05-21	clk: zynq: Factor out PLL driver	Soren Brinkmann	1	-0/+235