starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2017-06-20	clk: zx296718: export I2S mux clocks	Shawn Guo	1	-4/+4
2017-04-12	clk: zte: Mark pll config tables as const	Stephen Boyd	1	-2/+2
2017-04-12	clk: zte: add pll_vga clock for zx296718	Shawn Guo	1	-0/+24
2017-04-12	clk: zte: pd_bit is not 0 on zx296718	Shawn Guo	2	-2/+16
2017-04-12	clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks	Shawn Guo	1	-3/+3
2017-02-10	clk: zte: add i2s clocks for zx296718	Baoyou Xie	1	-0/+4
2017-01-10	clk: zte: add audio clocks for zx296718	Jun Nie	3	-0/+275
2017-01-10	clk: zx296718: do not panic on failure	Shawn Guo	1	-9/+18
2016-09-24	clk: zx296718: register driver earlier with core_initcall	Shawn Guo	1	-1/+5
2016-09-17	clk: zx: fix pointer case warnings	Arnd Bergmann	1	-10/+10
2016-09-17	clk: zx296718: use builtin_platform_driver to simplify the code	Wei Yongjun	1	-5/+1
2016-09-14	clk: zx: register ZX296718 clocks	Jun Nie	3	-0/+1050
2016-09-14	clk: zx: reform pll config info to ease code extension	Jun Nie	2	-9/+16
2016-04-16	clk: zte: Remove CLK_IS_ROOT	Stephen Boyd	1	-2/+1
2015-07-28	clk: zx: Constify parent names in clock init data	Jun Nie	1	-20/+20
2015-07-28	clk: zx: Add audio and GPIO clock for zx296702	Jun Nie	1	-2/+90
2015-07-28	clk: zx: Add audio div clock method for zx296702	Jun Nie	3	-3/+149
2015-06-12	clk: zx: add clock support to zx296702	Jun Nie	4	-0/+863