index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
tegra
Age
Commit message (
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)
Author
Files
Lines
2021-02-22
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
2
-4
/
+2
2021-02-21
Merge tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Linus Torvalds
5
-15
/
+75
2021-02-11
clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s...
Lee Jones
1
-0
/
+1
2021-02-11
clk: tegra: clk-tegra30: Remove unused variable 'reg'
Lee Jones
1
-4
/
+1
2021-01-12
clk: tegra30: Add hda clock default rates to clock driver
Peter Geis
1
-0
/
+2
2021-01-05
memory: tegra124-emc: Make driver modular
Dmitry Osipenko
5
-15
/
+75
2020-12-21
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
4
-6
/
+7
2020-12-10
clk: tegra: Fix duplicated SE clock entry
Dmitry Osipenko
2
-1
/
+2
2020-11-26
clk: tegra: bpmp: Clamp clock rates on requests
Sivaram Nair
1
-3
/
+3
2020-11-20
clk: tegra: Do not return 0 on failure
Nicolin Chen
1
-2
/
+2
2020-11-06
clk: tegra: Export Tegra20 EMC kernel symbols
Dmitry Osipenko
1
-0
/
+3
2020-10-22
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-1
/
+1
2020-09-24
clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()
Stephen Boyd
1
-1
/
+1
2020-09-21
clk: tegra: Fix missing prototype for tegra210_clk_register_emc()
Thierry Reding
1
-0
/
+2
2020-09-21
clk: tegra: Always program PLL_E when enabled
Thierry Reding
1
-3
/
+0
2020-09-21
clk: tegra: Capitalization fixes
Thierry Reding
1
-2
/
+2
2020-07-28
clk: tegra: pll: Improve PLLM enable-state detection
Dmitry Osipenko
1
-5
/
+15
2020-06-10
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
10
-32
/
+700
2020-05-13
clk: tegra: Fix initial rate for pll_a on Tegra124
Thierry Reding
1
-1
/
+1
2020-05-12
clk: tegra: Add Tegra210 CSI TPG clock gate
Sowjanya Komatineni
1
-0
/
+7
2020-05-12
clk: tegra30: Use custom CCLK implementation
Dmitry Osipenko
1
-2
/
+4
2020-05-12
clk: tegra20: Use custom CCLK implementation
Dmitry Osipenko
1
-2
/
+5
2020-05-12
clk: tegra: cclk: Add helpers for handling PLLX rate changes
Dmitry Osipenko
2
-0
/
+36
2020-05-12
clk: tegra: pll: Add pre/post rate-change hooks
Dmitry Osipenko
2
-1
/
+17
2020-05-12
clk: tegra: Add custom CCLK implementation
Dmitry Osipenko
3
-2
/
+188
2020-05-12
clk: tegra: Remove the old emc_mux clock for Tegra210
Joseph Lo
1
-19
/
+31
2020-05-12
clk: tegra: Implement Tegra210 EMC clock
Joseph Lo
3
-0
/
+373
2020-05-12
clk: tegra: Export functions for EMC clock scaling
Joseph Lo
1
-0
/
+26
2020-05-12
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Joseph Lo
1
-0
/
+11
2020-05-12
clk: tegra: Rename Tegra124 EMC clock source file
Thierry Reding
4
-6
/
+2
2020-03-25
clk: tegra: Use NULL for pointer initialization
Stephen Boyd
1
-1
/
+1
2020-03-12
clk: tegra: Remove audio clocks configuration from clock driver
Sowjanya Komatineni
5
-15
/
+10
2020-03-12
clk: tegra: Remove tegra_pmc_clk_init along with clk ids
Sowjanya Komatineni
9
-201
/
+19
2020-03-12
clk: tegra: Remove CLK_M_DIV fixed clocks
Sowjanya Komatineni
6
-45
/
+0
2020-03-12
clk: tegra: Fix Tegra PMC clock out parents
Sowjanya Komatineni
1
-6
/
+6
2020-03-12
clk: tegra: Add Tegra OSC to clock lookup
Sowjanya Komatineni
6
-0
/
+14
2020-03-12
clk: tegra: Add support for OSC_DIV fixed clocks
Sowjanya Komatineni
6
-0
/
+34
2020-02-01
Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', '...
Stephen Boyd
5
-11
/
+15
2020-01-10
clk: tegra20/30: Explicitly set parent clock for Video Decoder
Dmitry Osipenko
2
-2
/
+2
2020-01-10
clk: tegra20/30: Don't pre-initialize displays parent clock
Dmitry Osipenko
2
-4
/
+0
2020-01-10
clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul...
Dmitry Osipenko
1
-2
/
+7
2020-01-10
clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()
Sowjanya Komatineni
1
-2
/
+1
2020-01-08
clk: tegra: Mark fuse clock as critical
Stephen Warren
1
-1
/
+5
2019-12-24
clk: tegra: Fix double-free in tegra_clk_init()
Dmitry Osipenko
1
-1
/
+3
2019-11-14
clk: tegra: Use match_string() helper to simplify the code
YueHaibing
1
-8
/
+4
2019-11-11
clk: tegra: Fix build error without CONFIG_PM_SLEEP
YueHaibing
1
-0
/
+2
2019-11-11
clk: tegra: Optimize PLLX restore on Tegra20/30
Dmitry Osipenko
2
-18
/
+32
2019-11-11
clk: tegra: Add suspend and resume support on Tegra210
Sowjanya Komatineni
3
-4
/
+163
2019-11-11
clk: tegra: Share clk and rst register defines with Tegra clock driver
Sowjanya Komatineni
2
-45
/
+45
2019-11-11
clk: tegra: Use fence_udelay() during PLLU init
Sowjanya Komatineni
1
-4
/
+4
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