| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-12-15 | Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '... | Stephen Boyd | 10 | -32/+80 |
| 2018-12-15 | clk: tegra: Return the exact clock rate from clk_round_rate | Robert Yang | 1 | -3/+4 |
| 2018-12-15 | clk: tegra30: Use Tegra CPU powergate helper function | Jon Hunter | 1 | -3/+3 |
| 2018-12-15 | clk: tegra: Fix maximum audio sync clock for Tegra124/210 | Jon Hunter | 7 | -13/+37 |
| 2018-12-15 | clk: tegra: get rid of duplicate defines | Marcel Ziswiler | 1 | -3/+0 |
| 2018-11-29 | clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macro | Yangtao Li | 1 | -11/+1 |
| 2018-11-08 | clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC | Dmitry Osipenko | 1 | -0/+10 |
| 2018-11-08 | clk: tegra20: Turn EMC clock gate into divider | Dmitry Osipenko | 1 | -10/+26 |
| 2018-10-17 | clk: tegra210: Include size.h for compilation ease | Stephen Boyd | 1 | -0/+1 |
| 2018-10-17 | clk: tegra: Fixes for MBIST work around | Joseph Lo | 1 | -3/+3 |
| 2018-10-17 | clk: tegra: probe deferral error reporting | Marcel Ziswiler | 1 | -2/+6 |
| 2018-08-15 | Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',... | Stephen Boyd | 8 | -40/+343 |
| 2018-08-15 | Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te... | Stephen Boyd | 4 | -7/+15 |
| 2018-07-26 | clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks | Peter De-Schrijver | 3 | -15/+12 |
| 2018-07-25 | clk: tegra: Add sdmmc mux divider clock | Peter De-Schrijver | 3 | -0/+278 |
| 2018-07-25 | clk: tegra: Refactor fractional divider calculation | Peter De Schrijver | 4 | -25/+52 |
| 2018-07-25 | clk: tegra: Fix includes required by fence_udelay() | Aapo Vienamo | 1 | -0/+1 |
| 2018-07-09 | clk: tegra: emc: Avoid out-of-bounds bug | Dmitry Osipenko | 1 | -1/+1 |
| 2018-07-09 | clk: tegra: Mark Memory Controller clock as critical | Dmitry Osipenko | 1 | -2/+3 |
| 2018-07-09 | clk: tegra: Make vde a child of pll_c3 | Thierry Reding | 1 | -1/+1 |
| 2018-07-09 | clk: tegra: Make vic03 a child of pll_c3 | Thierry Reding | 1 | -0/+1 |
| 2018-07-09 | clk: tegra: bpmp: Don't crash when a clock fails to register | Mikko Perttunen | 1 | -3/+9 |
| 2018-06-13 | treewide: kzalloc() -> kcalloc() | Kees Cook | 1 | -3/+4 |
| 2018-06-04 | Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and... | Stephen Boyd | 1 | -31/+11 |
| 2018-06-02 | clk: tegra: no need to check return value of debugfs_create functions | Greg Kroah-Hartman | 1 | -31/+11 |
| 2018-05-18 | clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 | Dmitry Osipenko | 7 | -8/+39 |
| 2018-05-18 | clk: tegra20: Correct parents of CDEV1/2 clocks | Dmitry Osipenko | 1 | -4/+2 |
| 2018-05-18 | clk: tegra20: Add DEV1/DEV2 OSC dividers | Dmitry Osipenko | 1 | -0/+14 |
| 2018-03-12 | clk: tegra: Fix pll_u rate configuration | Marcel Ziswiler | 1 | -0/+2 |
| 2018-03-12 | clk: tegra: Specify VDE clock rate | Dmitry Osipenko | 4 | -1/+4 |
| 2018-03-12 | clk: tegra20: Correct PLL_C_OUT1 setup | Dmitry Osipenko | 1 | -3/+3 |
| 2018-03-12 | clk: tegra: Mark HCLK, SCLK and EMC as critical | Dmitry Osipenko | 8 | -36/+26 |
| 2018-03-08 | clk: tegra: MBIST work around for Tegra210 | Peter De Schrijver | 1 | -2/+342 |
| 2018-03-08 | clk: tegra: add fence_delay for clock registers | Peter De Schrijver | 1 | -0/+7 |
| 2018-03-08 | clk: tegra: Add la clock for Tegra210 | Peter De Schrijver | 1 | -0/+14 |
| 2017-11-18 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 13 | -66/+102 |
| 2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman | 2 | -0/+2 |
| 2017-11-01 | clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init() | Nicolin Chen | 1 | -2/+2 |
| 2017-11-01 | clk: tegra: dfll: Fix drvdata overwriting issue | Nicolin Chen | 3 | -13/+11 |
| 2017-11-01 | clk: tegra: Fix cclk_lp divisor register | Michał Mirosław | 1 | -1/+1 |
| 2017-11-01 | clk: tegra: Bump SCLK clock rate to 216 MHz | Dmitry Osipenko | 1 | -1/+1 |
| 2017-11-01 | clk: tegra: Use common definition of APBDMA clock gate | Dmitry Osipenko | 1 | -5/+1 |
| 2017-11-01 | clk: tegra: Correct parent of the APBDMA clock | Dmitry Osipenko | 1 | -1/+1 |
| 2017-11-01 | clk: tegra: Add AHB DMA clock entry | Dmitry Osipenko | 4 | -0/+4 |
| 2017-11-01 | clk: tegra: Mark APB clock as critical | Jon Hunter | 1 | -1/+1 |
| 2017-10-19 | clk: tegra: Make tegra_clk_pll_params __ro_after_init | Bhumika Goyal | 1 | -8/+8 |
| 2017-10-19 | clk: tegra: Fix sor1_out clock implementation | Thierry Reding | 2 | -16/+47 |
| 2017-10-19 | clk: tegra: Use tegra_clk_register_periph_data() | Thierry Reding | 4 | -13/+4 |
| 2017-10-19 | clk: tegra: Add peripheral clock registration helper | Thierry Reding | 2 | -0/+11 |
| 2017-10-19 | clk: tegra: Check BPMP response return code | Timo Alho | 1 | -5/+10 |
