| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-11-11 | clk: tegra: pllout: Save and restore pllout context | Sowjanya Komatineni | 1 | -0/+9 |
| 2019-11-11 | clk: tegra: divider: Save and restore divider rate | Sowjanya Komatineni | 1 | -0/+11 |
| 2019-11-11 | clk: tegra: Reimplement SOR clocks on Tegra210 | Thierry Reding | 1 | -16/+55 |
| 2019-11-11 | clk: tegra: Reimplement SOR clock on Tegra124 | Thierry Reding | 1 | -9/+13 |
| 2019-11-11 | clk: tegra: Rename sor0_lvds to sor0_out | Thierry Reding | 3 | -8/+8 |
| 2019-11-11 | clk: tegra: Move SOR0 implementation to Tegra124 | Thierry Reding | 2 | -8/+49 |
| 2019-11-11 | clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC | Thierry Reding | 2 | -2/+2 |
| 2019-11-11 | clk: tegra: Add Tegra20/30 EMC clock implementation | Dmitry Osipenko | 5 | -52/+339 |
| 2019-07-17 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 1 | -8/+12 |
| 2019-06-28 | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/... | Linus Torvalds | 1 | -0/+2 |
| 2019-06-26 | clk: tegra: Do not enable PLL_RE_VCO on Tegra210 | Thierry Reding | 1 | -1/+0 |
| 2019-06-26 | clk: tegra: Warn if an enabled PLL is in IDDQ | Thierry Reding | 1 | -1/+5 |
| 2019-06-26 | clk: tegra: Do not warn unnecessarily | Thierry Reding | 1 | -2/+3 |
| 2019-06-26 | clk: tegra210: fix PLLU and PLLU_OUT1 | JC Kuo | 1 | -4/+4 |
| 2019-06-19 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 | Thomas Gleixner | 1 | -4/+1 |
| 2019-06-14 | clk: tegra210: Fix default rates for HDA clocks | Jon Hunter | 1 | -0/+2 |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 | Thomas Gleixner | 1 | -9/+1 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 | Thomas Gleixner | 20 | -240/+20 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner | 5 | -49/+5 |
| 2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner | 1 | -0/+1 |
| 2019-05-15 | clk: Remove io.h from clk-provider.h | Stephen Boyd | 4 | -0/+4 |
| 2019-05-07 | Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and... | Stephen Boyd | 4 | -40/+77 |
| 2019-05-07 | Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-... | Stephen Boyd | 1 | -1/+1 |
| 2019-04-25 | clk: tegra: divider: Mark Memory Controller clock as read-only | Dmitry Osipenko | 1 | -1/+2 |
| 2019-04-25 | clk: tegra: emc: Replace BUG() with WARN_ONCE() | Dmitry Osipenko | 1 | -1/+4 |
| 2019-04-25 | clk: tegra: emc: Fix EMC max-rate clamping | Dmitry Osipenko | 1 | -7/+10 |
| 2019-04-25 | clk: tegra: emc: Support multiple RAM codes | Dmitry Osipenko | 1 | -14/+23 |
| 2019-04-25 | clk: tegra: emc: Don't enable EMC clock manually | Dmitry Osipenko | 1 | -2/+0 |
| 2019-04-25 | clk: tegra124: Remove lock-enable bit from PLLM | Dmitry Osipenko | 1 | -2/+1 |
| 2019-04-25 | clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider | Dmitry Osipenko | 1 | -2/+2 |
| 2019-04-23 | clk: core: replace clk_{readl,writel} with {readl,writel} | Jonas Gorski | 2 | -5/+5 |
| 2019-04-20 | clk: tegra: Don't enable already enabled PLLs | Dmitry Osipenko | 1 | -13/+37 |
| 2019-04-11 | clk: tegra: Make tegra_clk_super_mux_ops static | YueHaibing | 1 | -1/+1 |
| 2019-03-14 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 1 | -9/+9 |
| 2019-03-08 | Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ... | Stephen Boyd | 1 | -9/+9 |
| 2019-02-22 | clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings | YueHaibing | 1 | -9/+9 |
| 2019-02-18 | clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static | Wei Yongjun | 1 | -1/+1 |
| 2019-02-15 | Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Arnd Bergmann | 7 | -98/+913 |
| 2019-02-06 | clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 | Peter De Schrijver | 2 | -1/+6 |
| 2019-02-06 | clk: tegra: dfll: add CVB tables for Tegra210 | Joseph Lo | 2 | -0/+427 |
| 2019-02-06 | clk: tegra: dfll: round down voltages based on alignment | Joseph Lo | 1 | -8/+13 |
| 2019-02-06 | clk: tegra: dfll: support PWM regulator control | Joseph Lo | 1 | -67/+377 |
| 2019-02-06 | clk: tegra: dfll: CVB calculation alignment with the regulator | Joseph Lo | 4 | -14/+59 |
| 2019-02-06 | clk: tegra: dfll: registration for multiple SoCs | Peter De Schrijver | 1 | -11/+34 |
| 2019-01-09 | clk: tegra: dfll: Fix a potential Oop in remove() | Dan Carpenter | 1 | -1/+3 |
| 2018-12-15 | Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '... | Stephen Boyd | 10 | -32/+80 |
| 2018-12-15 | clk: tegra: Return the exact clock rate from clk_round_rate | Robert Yang | 1 | -3/+4 |
| 2018-12-15 | clk: tegra30: Use Tegra CPU powergate helper function | Jon Hunter | 1 | -3/+3 |
| 2018-12-15 | clk: tegra: Fix maximum audio sync clock for Tegra124/210 | Jon Hunter | 7 | -13/+37 |
| 2018-12-15 | clk: tegra: get rid of duplicate defines | Marcel Ziswiler | 1 | -3/+0 |
