starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2015-12-17	clk: tegra: Add support for Tegra210 clocks	Rhyland Klein	1	-0/+3
2015-12-17	clk: tegra: Add Super Gen5 Logic	Bill Huang	1	-0/+3
2015-12-17	clk: tegra: pll: Add logic for SS	Bill Huang	1	-0/+4
2015-12-17	clk: tegra: pll: Add dyn_ramp callback	Rhyland Klein	1	-0/+4
2015-12-17	clk: tegra: pll: Add Set_default logic	Bill Huang	1	-0/+11
2015-12-17	clk: tegra: pll: Adjust vco_min if SDM present	Bill Huang	1	-0/+4
2015-12-17	clk: tegra: pll: Add support for PLLMB for Tegra210	Rhyland Klein	1	-0/+9
2015-12-17	clk: tegra: pll: Add specialized logic for Tegra210	Rhyland Klein	1	-0/+24
2015-11-20	clk: tegra: pll: Add code to handle if resets are supported by PLL	Bill Huang	1	-0/+4
2015-11-20	clk: tegra: pll: Add logic for out-of-table rates for T210	Rhyland Klein	1	-0/+13
2015-11-20	clk: tegra: pll: Add logic for handling SDM data	Rhyland Klein	1	-1/+14
2015-11-20	clk: tegra: pll: Change misc_reg count from 3 to 6	Bill Huang	1	-1/+3
2015-11-20	clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header	Rhyland Klein	1	-0/+1
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding	1	-1/+1
2015-10-20	clk: tegra: Modify tegra_audio_clk_init to accept more plls	Rhyland Klein	1	-1/+17
2015-10-20	clk: tegra: Update struct tegra_clk_pll_params kerneldoc	Thierry Reding	1	-3/+15
2015-10-20	clk: tegra: Fix comments for structure definitions	Rhyland Klein	1	-37/+37
2015-07-16	clk: tegra: Introduce ability for SoC-specific reset control callbacks	Mikko Perttunen	1	-0/+3
2015-05-13	clk: tegra: EMC clock driver depends on EMC driver	Thierry Reding	1	-0/+9
2015-05-13	clk: tegra: Add EMC clock driver	Mikko Perttunen	1	-0/+3
2015-04-10	clk: tegra: Model oscillator as clock	Thierry Reding	1	-4/+4
2015-04-10	clk: tegra: Fix typo tabel -> table	Thierry Reding	1	-1/+1
2014-11-26	clk: tegra: Implement memory-controller clock	Thierry Reding	1	-0/+2
2013-12-12	clk: tegra: remove legacy reset APIs	Stephen Warren	1	-1/+0
2013-12-12	clk: tegra: implement a reset driver	Stephen Warren	1	-1/+1
2013-11-26	clk: tegra: add TEGRA_PERIPH_NO_GATE	Peter De Schrijver	1	-0/+1
2013-11-26	clk: tegra: add locking to periph clks	Peter De Schrijver	1	-4/+6
2013-11-26	clk: tegra: Add support for PLLSS	Peter De Schrijver	1	-0/+5
2013-11-26	clk: tegra: introduce common gen4 super clock	Peter De Schrijver	1	-0/+3
2013-11-26	clk: tegra: move PMC, fixed clocks to common files	Peter De Schrijver	1	-0/+7
2013-11-26	clk: tegra: move periph clocks to common file	Peter De Schrijver	1	-2/+9
2013-11-26	clk: tegra: move audio clk to common file	Peter De Schrijver	1	-0/+4
2013-11-26	clk: tegra: add clkdev registration infra	Peter De Schrijver	1	-0/+7
2013-11-26	clk: tegra: add common infra for DT clocks	Peter De Schrijver	1	-0/+7
2013-11-26	clk: tegra: move fields to tegra_clk_pll_params	Peter De Schrijver	1	-23/+11
2013-11-26	clk: tegra: Add TEGRA_PERIPH_NO_DIV flag	Peter De Schrijver	1	-0/+1
2013-11-26	clk: tegra: common periph_clk_enb_refcnt and clks	Peter De Schrijver	1	-7/+9
2013-11-26	clk: tegra: simplify periph clock data	Peter De Schrijver	1	-8/+9
2013-06-18	clk: tegra: T114: add DFLL DVCO reset control	Paul Walmsley	1	-0/+2
2013-06-18	clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL	Paul Walmsley	1	-0/+4
2013-06-12	clk: tegra: Add fields for override bits	Peter De Schrijver	1	-0/+8
2013-06-12	clk: tegra: allow PLL m,n,p init from SoC files	Peter De Schrijver	1	-12/+20
2013-05-31	clk: tegra: Use common of_clk_init function	Prashant Gaikwad	1	-18/+0
2013-04-05	clk: tegra: devicetree match for nvidia,tegra114-car	Peter De Schrijver	1	-0/+6
2013-04-05	clk: tegra: Workaround for Tegra114 MSENC problem	Peter De Schrijver	1	-0/+2
2013-04-05	clk: tegra: Add flags to tegra_clk_periph()	Peter De Schrijver	1	-3/+6
2013-04-05	clk: tegra: Add new fields and PLL types for Tegra114	Peter De Schrijver	1	-1/+49
2013-04-05	clk: tegra: move from a lock bit idx to a lock mask	Peter De Schrijver	1	-1/+1
2013-04-05	clk: tegra: Add PLL post divider table	Peter De Schrijver	1	-0/+13
2013-04-05	clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE	Peter De Schrijver	1	-0/+2