index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
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tree
commit
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path:
root
/
drivers
/
clk
/
tegra
/
clk.h
Age
Commit message (
Expand
)
Author
Files
Lines
2013-11-26
clk: tegra: Add support for PLLSS
Peter De Schrijver
1
-0
/
+5
2013-11-26
clk: tegra: introduce common gen4 super clock
Peter De Schrijver
1
-0
/
+3
2013-11-26
clk: tegra: move PMC, fixed clocks to common files
Peter De Schrijver
1
-0
/
+7
2013-11-26
clk: tegra: move periph clocks to common file
Peter De Schrijver
1
-2
/
+9
2013-11-26
clk: tegra: move audio clk to common file
Peter De Schrijver
1
-0
/
+4
2013-11-26
clk: tegra: add clkdev registration infra
Peter De Schrijver
1
-0
/
+7
2013-11-26
clk: tegra: add common infra for DT clocks
Peter De Schrijver
1
-0
/
+7
2013-11-26
clk: tegra: move fields to tegra_clk_pll_params
Peter De Schrijver
1
-23
/
+11
2013-11-26
clk: tegra: Add TEGRA_PERIPH_NO_DIV flag
Peter De Schrijver
1
-0
/
+1
2013-11-26
clk: tegra: common periph_clk_enb_refcnt and clks
Peter De Schrijver
1
-7
/
+9
2013-11-26
clk: tegra: simplify periph clock data
Peter De Schrijver
1
-8
/
+9
2013-06-18
clk: tegra: T114: add DFLL DVCO reset control
Paul Walmsley
1
-0
/
+2
2013-06-18
clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
Paul Walmsley
1
-0
/
+4
2013-06-12
clk: tegra: Add fields for override bits
Peter De Schrijver
1
-0
/
+8
2013-06-12
clk: tegra: allow PLL m,n,p init from SoC files
Peter De Schrijver
1
-12
/
+20
2013-05-31
clk: tegra: Use common of_clk_init function
Prashant Gaikwad
1
-18
/
+0
2013-04-05
clk: tegra: devicetree match for nvidia,tegra114-car
Peter De Schrijver
1
-0
/
+6
2013-04-05
clk: tegra: Workaround for Tegra114 MSENC problem
Peter De Schrijver
1
-0
/
+2
2013-04-05
clk: tegra: Add flags to tegra_clk_periph()
Peter De Schrijver
1
-3
/
+6
2013-04-05
clk: tegra: Add new fields and PLL types for Tegra114
Peter De Schrijver
1
-1
/
+49
2013-04-05
clk: tegra: move from a lock bit idx to a lock mask
Peter De Schrijver
1
-1
/
+1
2013-04-05
clk: tegra: Add PLL post divider table
Peter De Schrijver
1
-0
/
+13
2013-04-05
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
Peter De Schrijver
1
-0
/
+2
2013-04-05
clk: tegra: Add TEGRA_PLL_BYPASS flag
Peter De Schrijver
1
-0
/
+2
2013-04-05
clk: tegra: Refactor PLL programming code
Peter De Schrijver
1
-3
/
+6
2013-04-05
clk: tegra: defer application of init table
Stephen Warren
1
-0
/
+3
2013-03-23
clk: add table lookup to mux
Peter De Schrijver
1
-8
/
+19
2013-01-28
clk: tegra: add clock support for Tegra30
Prashant Gaikwad
1
-0
/
+6
2013-01-28
clk: tegra: add clock support for Tegra20
Prashant Gaikwad
1
-0
/
+6
2013-01-28
clk: tegra: add Tegra specific clocks
Prashant Gaikwad
1
-0
/
+490