index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
tegra
/
clk-tegra20.c
Age
Commit message (
Expand
)
Author
Files
Lines
2016-04-28
treewide: Fix typos in printk
Masanari Iida
1
-1
/
+1
2016-03-03
clk: tegra: Remove CLK_IS_ROOT
Stephen Boyd
1
-6
/
+4
2015-11-20
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate
Rhyland Klein
1
-72
/
+78
2015-11-20
clk: tegra: pll: Don't unconditionally set LOCK flags
Rhyland Klein
1
-8
/
+10
2015-11-20
clk: tegra: Constify pdiv-to-hw mappings
Thierry Reding
1
-1
/
+1
2015-11-18
clk: tegra: Format tables consistently
Thierry Reding
1
-143
/
+134
2015-11-18
clk: tegra: Miscellaneous coding style cleanups
Thierry Reding
1
-3
/
+2
2015-07-20
clk: tegra: Properly include clk.h
Stephen Boyd
1
-1
/
+0
2014-11-26
clk: tegra: Implement memory-controller clock
Thierry Reding
1
-1
/
+7
2014-02-17
clk: tegra: Add missing Tegra20 fuse clks
Peter De Schrijver
1
-0
/
+2
2013-12-12
clk: tegra: remove bogus PCIE_XCLK
Stephen Warren
1
-6
/
+0
2013-12-12
clk: tegra: implement a reset driver
Stephen Warren
1
-1
/
+2
2013-11-26
clk: tegra: add FUSE clock device
Alexandre Courbot
1
-0
/
+1
2013-11-26
clk: tegra: move tegra20 to common infra
Peter De Schrijver
1
-402
/
+255
2013-11-26
clk: tegra: move periph clocks to common file
Peter De Schrijver
1
-2
/
+2
2013-11-26
clk: tegra: move fields to tegra_clk_pll_params
Peter De Schrijver
1
-17
/
+27
2013-11-26
clk: tegra: common periph_clk_enb_refcnt and clks
Peter De Schrijver
1
-27
/
+9
2013-11-26
clk: tegra: simplify periph clock data
Peter De Schrijver
1
-138
/
+82
2013-08-19
clk: add CLK_SET_RATE_NO_REPARENT flag
James Hogan
1
-2
/
+4
2013-08-09
clk: tegra20: Fix incorrect placement of __initdata
Sachin Kamat
1
-1
/
+1
2013-05-31
clk: tegra: Use common of_clk_init function
Prashant Gaikwad
1
-1
/
+2
2013-05-21
clk: tegra: add ac97 controller clock
Lucas Stach
1
-0
/
+8
2013-05-21
clk: tegra: remove USB from clk init table
Lucas Stach
1
-3
/
+0
2013-05-04
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Linus Torvalds
1
-85
/
+99
2013-05-02
Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/g...
Linus Torvalds
1
-34
/
+2
2013-04-09
Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann
1
-34
/
+2
2013-04-05
clk: tegra: Add flags to tegra_clk_periph()
Peter De Schrijver
1
-1
/
+1
2013-04-05
clk: tegra: move from a lock bit idx to a lock mask
Peter De Schrijver
1
-10
/
+10
2013-04-05
clk: tegra: Add PLL post divider table
Peter De Schrijver
1
-0
/
+7
2013-04-05
clk: tegra: Refactor PLL programming code
Peter De Schrijver
1
-72
/
+72
2013-04-05
clk: tegra: defer application of init table
Stephen Warren
1
-1
/
+6
2013-04-05
clk: tegra: Fix cdev1 and cdev2 IDs
Prashant Gaikwad
1
-1
/
+1
2013-04-05
clk: tegra: Make gr2d and gr3d clocks children of pll_c
Thierry Reding
1
-0
/
+2
2013-04-05
Merge branch 'for-3.10/soc' into for-3.10/clk
Stephen Warren
1
-34
/
+2
2013-04-01
clk: tegra: Allow PLLE training to succeed
Thierry Reding
1
-1
/
+1
2013-03-12
clk: tegra: No 7.1 super clk dividers on Tegra20
Peter De Schrijver
1
-34
/
+2
2013-03-05
clk: Tegra: Remove duplicate smp_twd clock
Prashant Gaikwad
1
-1
/
+0
2013-02-13
clk: tegra: initialise parent of uart clocks
Laxman Dewangan
1
-2
/
+5
2013-02-13
clk: tegra: fix driver to match DT binding
Stephen Warren
1
-2
/
+2
2013-02-12
clk: tegra: Add missing spinlock for hclk and pclk
Peter De Schrijver
1
-4
/
+7
2013-01-28
clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops
Joseph Lo
1
-0
/
+93
2013-01-28
clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s
Prashant Gaikwad
1
-17
/
+0
2013-01-28
clk: tegra: add clock support for Tegra20
Prashant Gaikwad
1
-0
/
+1273