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path: root/drivers/clk/tegra/clk-tegra124.c
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2021-01-05memory: tegra124-emc: Make driver modularDmitry Osipenko1-3/+23
Add modularization support to the Tegra124 EMC driver, which now can be compiled as a loadable kernel module. Note that EMC clock must be registered at clk-init time, otherwise PLLM will be disabled as unused clock at boot time if EMC driver is compiled as a module. Hence add a prepare/complete callbacks. similarly to what is done for the Tegra20/30 EMC drivers. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201228154920.18846-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-13clk: tegra: Fix initial rate for pll_a on Tegra124Thierry Reding1-1/+1
pll_a_out0 and the I2S clocks are already configured to default to rates corresponding to a 44.1 kHz sampling rate, but the pll_a configuration was set to a default that is not listed in the frequency table, which caused the PLL code to compute an invalid configuration. As a result of this invalid configuration, Jetson TK1 fails to resume from suspend. This used to get papered over because the ASoC driver would force audio clocks to a 44.1 kHz configuration on boot. However, that's not really necessary and was hence removed in commit ff5d18cb04f4 ("ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init()"). Fix the initial rate for pll_a so that it matches the 44.1 kHz entry in the pll_a frequency table. Fixes: ff5d18cb04f4 ("ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init()") Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lkml.kernel.org/r/20200505071655.644773-1-thierry.reding@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-12clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni1-3/+2
Current clock driver enables PLLA, cdev1 on Tegra20 and extern1 on Tegra30 and above as a part of clocks init and there is no need to have these audio clocks enabled by the clock driver. extern1 is used as parent for clk_out_1 and clk_out_1 is dedicated for audio mclk on Tegra30 and above Tegra platforms and these clocks are taken care by ASoC driver. So, this patch removes audio related clocks configuration from clock init of Tegra20 and above. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni1-23/+10
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2, clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct PMC register access during clk_ops and these PMC register read and write access will not happen when PMC is in secure mode. Any direct PMC register access from non-secure world will not go through. All the PMC clocks are moved to Tegra PMC driver with PMC as a clock provider. This patch removes tegra_pmc_clk_init along with corresponding clk ids from Tegra clock driver. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni1-4/+0
Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible parents of PMC clocks for Tegra30 through Tegra210. Tegra PMC clock parents are changed to use OSC_DIV clocks. So, this patch removes CLK_M_DIV fixed clocks Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni1-0/+2
OSC is one of the parent for Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3. This patch adds Tegra OSC to clock lookup. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni1-0/+4
Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks from the OSC pads. This patch adds support for these clocks. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding1-9/+13
In order to allow the display driver to deal uniformly with all SOR generations, implement the SOR clocks in a way that is compatible with Tegra186 and later. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding1-6/+6
This makes Tegra124 and Tegra210 consistent with subsequent Tegra generations. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding1-0/+49
The SOR0 clock on Tegra210 is very different from the SOR0 clock found on Tegra124. Move the Tegra124 implementation to the Tegra124 driver so that a custom implementation can be provided on Tegra210 without clashing with the existing clock. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' ↵Stephen Boyd1-2/+1
and 'clk-spdx' into clk-next - Support for STM32F769 - Rework AT91 sckc DT bindings - Fix slow RC oscillator issue on sama5d3 - AT91 sam9x60 PMC support - SiFive FU540 PRCI and PLL support * clk-stm32f4: clk: stm32mp1: Add ddrperfm clock clk: stm32: Introduce clocks of STM32F769 board * clk-tegra: clk: tegra: divider: Mark Memory Controller clock as read-only clk: tegra: emc: Replace BUG() with WARN_ONCE() clk: tegra: emc: Fix EMC max-rate clamping clk: tegra: emc: Support multiple RAM codes clk: tegra: emc: Don't enable EMC clock manually clk: tegra124: Remove lock-enable bit from PLLM clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider clk: tegra: Don't enable already enabled PLLs * clk-at91: clk: at91: Mark struct clk_range as const clk: at91: add sam9x60 pmc driver dt-bindings: clk: at91: add bindings for SAM9X60 pmc clk: at91: add sam9x60 PLL driver clk: at91: master: Add sam9x60 support clk: at91: usb: Add sam9x60 support clk: at91: allow configuring generated PCR layout clk: at91: allow configuring peripheral PCR layout clk: at91: sckc: handle different RC startup time clk: at91: modernize sckc binding dt-bindings: clock: at91: new sckc bindings * clk-sifive-fu540: clk: sifive: add a driver for the SiFive FU540 PRCI IP block clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver * clk-spdx: clk: sunxi-ng: Use the correct style for SPDX License Identifier clk: sprd: Use the correct style for SPDX License Identifier clk: renesas: Use the correct style for SPDX License Identifier clk: qcom: Use the correct style for SPDX License Identifier clk: davinci: Use the correct style for SPDX License Identifier clk: actions: Use the correct style for SPDX License Identifier
2019-04-25clk: tegra124: Remove lock-enable bit from PLLMDmitry Osipenko1-2/+1
According to the Tegra124 TRM documentation, PLLM_MISC2 register doesn't have the lock-enable bit as well as any other PLLM-related register. Hence PLLM re-locking can't be initiated by software. The incorrect bit setting should have been harmless since that bit is undefined according to TRM. Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski1-2/+2
Now that clk_{readl,writel} is just an alias for {readl,writel}, we can switch all users of clk_* to use the accessors directly and remove the helpers. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> [sboyd@kernel.org: Also convert renesas file so that this can be compile independently] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-15clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter1-1/+8
The maximum frequency supported for I2S on Tegra124 and Tegra210 is 24.576MHz (as stated in the Tegra TK1 data sheet for Tegra124 and the Jetson TX1 module data sheet for Tegra210). However, the maximum I2S frequency is limited to 24MHz because that is the maximum frequency of the audio sync clock. Increase the maximum audio sync clock frequency to 24.576MHz for Tegra124 and Tegra210 in order to support 24.576MHz for I2S. Update the tegra_clk_register_sync_source() function so that it does not set the initial rate for the sync clocks and use the clock init tables to set the initial rate instead. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-09clk: tegra: Make vde a child of pll_c3Thierry Reding1-1/+1
The current default is to leave the VDE clock's parent at the default, which is clk_m. However, that is not a configuration that will allow the VDE to function. Reparent it to pll_c3 instead to make sure the hardware can actually decode video content. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-09clk: tegra: Make vic03 a child of pll_c3Thierry Reding1-0/+1
By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko1-1/+1
CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user may expect parent clock to be enabled by the child, so let's return -EPROBE_DEFER till parent clock appears. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko1-1/+1
Currently VDE clock rate is determined by clock config left from bootloader, let's not rely on it and explicitly specify the clock rate in the CCF driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko1-4/+3
Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks as critical. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: <stable@vger.kernel.org> # v4.16 Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver1-0/+1
This clock is used to clock the HDMI CEC interface. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker1-154/+2
Move the UTMI PLL initialization code form clk-tegra<chip>.c files into clk-pll.c. UTMI PLL was being configured and set in HW control right after registration. However, when the clock init_table is processed and child clks of PLLU are enabled, it will call in and enable PLLU as well, and initiate SW enabling sequence even though PLLU is already in HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. Doing the initialization once during pllu_enable means we configure it properly into HW control. A side effect of the commonization/localization of the UTMI PLL init code, is that it corrects some errors that were present for earlier generations. For instance, in clk-tegra124.c, it used to have: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) when the correct shift to use is present in the new version: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) which matches the Tegra124 TRM register definition. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> [rklein: Merged in some later fixes for potential deadlocks] Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding: coding style bike-shedding, remove unused variable] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding1-0/+4
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have a gate bit in the peripheral clock registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein1-30/+63
This removes the conversion from pdiv to hw, which is already taken care of by _get_table_rate before this code is run. This avoids incorrectly converting pdiv to hw twice and getting the wrong hw value. Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while setting all the other fields. In order to prevent regressions on earlier SoC generations, all of the frequency tables need to be updated so that they contain the actual divider values. If they contain hardware values these would be converted to hardware values again, yielding the wrong value. Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding@nvidia.com: fix regressions on earlier SoC generations] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein1-9/+15
SoC specific drivers should define the appropriate flags for each PLL rather than relying on the registration functions to automatically set flags on their behalf. This will properly allow for changes between SoC generations where flags might be different and allow sharing the same logic functions. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding1-5/+5
This is static data that is never modified, so make it const. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-18clk: tegra: Format tables consistentlyThierry Reding1-184/+186
Use spaces around { and } and pad values so that the cells are properly aligned. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding1-3/+3
Use unsigned int for loop variables that can never become negative and remove a couple of gratuitous blank lines. Also use single spaces around operators and use a single space instead of a tab to separate comments from code. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-18clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding1-1/+1
The OSC_FREQ field of the OSC_CTRL register uses the value 12 for an oscillator frequency of 26 MHz, not 260 MHz. This isn't really critical because I don't think boards with such an oscillator have ever existed, much less been supported upstream. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein1-1/+7
tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-26clk: tegra: Fix some static checker problemsStephen Boyd1-4/+4
The latest Tegra clk pull had some problems. Fix them. drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static? drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td->i2c_lut[0]' is never less than zero. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-26Merge tag 'tegra-for-4.3-clk' of ↵Stephen Boyd1-0/+82
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.3-rc1 This contains the DFLL driver needed to implement CPU frequency scaling on Tegra.
2015-07-20clk: tegra: Properly include clk.hStephen Boyd1-1/+0
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. Also add in a clkdev.h include that was missing in a file using clkdev APIs. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-16clk: tegra: Save/restore CCLKG_BURST_POLICY on suspendTuomas Tynkkynen1-0/+14
Save and restore this register since the LP1 restore assembly routines fiddle with it. Otherwise the CPU would keep running on PLLX after resume from suspend even when DFLL was the original clocksource. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16clk: tegra: Add DFLL DVCO reset control for Tegra124Paul Walmsley1-0/+68
The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and saving hours of debugging time. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> [ttynkkynen: ported to tegra124 from tegra114] Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> [mikko.perttunen: ported to special reset callback] Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-13clk: tegra: Set the EMC clock as the parent of the MC clockTomeu Vizoso1-12/+1
On Tegra124, as we now have a proper driver for the EMC. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-13clk: tegra: Add EMC clock driverMikko Perttunen1-1/+4
The driver is currently only tested on Tegra124 Jetson TK1, but should work with other Tegra124 boards, provided that correct EMC tables are provided through the device tree. Older chip models have differing timing change sequences, so they are not currently supported. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> [treding@nvidia.com: use more consistent function names] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-13clk: tegra: Remove old Tegra124 EMC clockMikko Perttunen1-1/+0
This clock has never been able to do anything. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10clk: tegra: Use the proper parent for plld_dsiThierry Reding1-6/+8
The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10clk: tegra: Model oscillator as clockThierry Reding1-1/+2
Currently the Tegra clock driver simplifies the clock tree somewhat by taking advantage of the fact that clk_m runs at the same frequency as the oscillator. While that's true on all currently supported SoCs, it does not apply to Tegra210 anymore. On Tegra210 clk_m is typically divided down from the oscillator frequency. To support that setup, add a separate clock for the oscillator that both clk_m and pll_ref derive from. Modify the tegra_osc_clk_init() function to take an additional divider parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210 will read the divider from a register in the clock & reset controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10clk: tegra: Enable HDA to HDMI clocks on Tegra124Dylan Reid1-0/+5
Add the clocks used for HDMI audio played through the HDA controller. Initialize the codec clock to 48Mhz and the HDA clock to 102MHz per the TRM. Signed-off-by: Dylan Reid <dgreid@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang1-20/+16
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
2015-02-02clk: tegra: Add support for the Tegra132 CAR IP blockPaul Walmsley1-9/+121
Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch mostly deals with the small differences. Since Tegra132 contains many of the same PLL clock sources used on Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when the kernel is configured to include Tegra132 support. This patch is based on several patches from others: 1. a patch from Peter De Schrijver: http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html 2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and 3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132"). Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Bill Huang <bilhuang@nvidia.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org>
2015-02-02clk: tegra124: Add init data for dsi lp clocksSean Paul1-0/+2
Set the parent of the dsi lp clocks to pll_p and the rate to 68MHz. The default parent is clk_m and rate is 12MHz, this is too slow to receive data from the peripheral. Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz will suffice. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding1-1/+6
The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-09-18clk: tegra124: Add PLL_M_UD and PLL_C_UD clocksMikko Perttunen1-0/+8
These clocks are used as parents for some EMC timings. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
2014-06-27clk: tegra124: init table updatesPeter De Schrijver1-0/+6
Ensure some clocks critical for system operation are always. Also enable csite for JTAG debugging and set the tsensor and soc_therm clock frequencies for the upcoming soctherm driver. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-06-25clk: tegra: Add SATA clocks to Tegra124 initialization tableMikko Perttunen1-0/+2
This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization table. The clocks are needed for working SATA support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2014-06-25clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver1-1/+1
vi_sensor and vi_sensor2 have a wrong hw clkid on Tegra124. Fix this by correcting the hw clkid for Tegra124 and creating the Tegra114 vi_sensor clock from its own data. Tegra124 was also using the wrong internal clock id. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-05-23clk: tegra: Initialize xusb clocksAndrew Bresticker1-0/+6
Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-23 12:21:54 +0300