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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
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path:
root
/
drivers
/
clk
/
tegra
/
clk-tegra114.c
Age
Commit message (
Expand
)
Author
Files
Lines
2016-03-03
clk: tegra: Remove CLK_IS_ROOT
Stephen Boyd
1
-2
/
+1
2015-11-20
clk: tegra: pll: Update PLLM handling
Danny Huang
1
-1
/
+2
2015-11-20
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate
Rhyland Klein
1
-51
/
+71
2015-11-20
clk: tegra: pll: Don't unconditionally set LOCK flags
Rhyland Klein
1
-10
/
+13
2015-11-20
clk: tegra: Constify pdiv-to-hw mappings
Thierry Reding
1
-4
/
+4
2015-11-18
clk: tegra: Format tables consistently
Thierry Reding
1
-136
/
+137
2015-11-18
clk: tegra: Miscellaneous coding style cleanups
Thierry Reding
1
-6
/
+6
2015-11-18
clk: tegra: Fix 26 MHz oscillator frequency
Thierry Reding
1
-1
/
+1
2015-10-20
clk: tegra: Modify tegra_audio_clk_init to accept more plls
Rhyland Klein
1
-1
/
+7
2015-07-20
clk: tegra: Properly include clk.h
Stephen Boyd
1
-2
/
+0
2015-04-10
clk: tegra: Use generic tegra_osc_clk_init() on Tegra114
Thierry Reding
1
-31
/
+3
2015-04-10
clk: tegra: Various whitespace cleanups
Thierry Reding
1
-1
/
+1
2015-02-02
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
Mark Zhang
1
-2
/
+8
2014-11-26
clk: tegra: Implement memory-controller clock
Thierry Reding
1
-1
/
+6
2014-06-25
clk: tegra: fix vi_sensor clocks on Tegra124
Peter De Schrijver
1
-1
/
+30
2014-05-23
clk: tegra: Initialize xusb clocks
Andrew Bresticker
1
-1
/
+6
2014-05-23
clk: tegra: Fix xusb_hs_src clock hierarchy
Andrew Bresticker
1
-10
/
+5
2014-02-17
clk: tegra: fix sdmmc clks on Tegra1x4
Andrew Bresticker
1
-4
/
+4
2013-12-12
clk: tegra: implement a reset driver
Stephen Warren
1
-1
/
+2
2013-11-26
clk: tegra: Initialize DSI low-power clocks
Thierry Reding
1
-0
/
+2
2013-11-26
clk: tegra: add FUSE clock device
Alexandre Courbot
1
-0
/
+1
2013-11-26
clk: tegra114: Initialize clocks needed for HDMI
Mikko Perttunen
1
-0
/
+2
2013-11-26
clk: tegra: introduce common gen4 super clock
Peter De Schrijver
1
-74
/
+2
2013-11-26
clk: tegra: move PMC, fixed clocks to common files
Peter De Schrijver
1
-74
/
+1
2013-11-26
clk: tegra: move periph clocks to common file
Peter De Schrijver
1
-574
/
+17
2013-11-26
clk: tegra: move audio clk to common file
Peter De Schrijver
1
-208
/
+182
2013-11-26
clk: tegra: add clkdev registration infra
Peter De Schrijver
1
-159
/
+163
2013-11-26
clk: tegra: move fields to tegra_clk_pll_params
Peter De Schrijver
1
-31
/
+43
2013-11-26
clk: tegra: use pll_ref as the pll_e parent
Peter De Schrijver
1
-1
/
+2
2013-11-26
clk: tegra: move some PLLC and PLLXC init to clk-pll.c
Peter De Schrijver
1
-89
/
+20
2013-11-26
clk: tegra: common periph_clk_enb_refcnt and clks
Peter De Schrijver
1
-41
/
+16
2013-11-26
clk: tegra: simplify periph clock data
Peter De Schrijver
1
-235
/
+141
2013-11-26
clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3d
Thierry Reding
1
-4
/
+4
2013-11-26
clk: tegra: Set the clk parent of host1x to pll_p
Andrew Chew
1
-0
/
+1
2013-11-26
clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks
Peter De Schrijver
1
-24
/
+29
2013-11-25
clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2
Mark Zhang
1
-0
/
+3
2013-11-25
clk: tegra: Fix vde/2d/3d clock src offset
Mark Zhang
1
-10
/
+3
2013-11-25
clk: tegra: Correct sbc mux width & parent
Mark Zhang
1
-6
/
+6
2013-11-25
clk: tegra: replace enum tegra114_clk by binding header
Peter De Schrijver
1
-233
/
+198
2013-09-10
Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux
Linus Torvalds
1
-13
/
+25
2013-08-19
clk: add CLK_SET_RATE_NO_REPARENT flag
James Hogan
1
-12
/
+24
2013-08-12
clk: tegra114: add LP1 suspend/resume support
Joseph Lo
1
-0
/
+12
2013-08-09
clk: tegra114: Fix incorrect placement of __initdata
Sachin Kamat
1
-1
/
+1
2013-07-19
clk: tegra: add suspend/resume function for tegra_cpu_car_ops
Joseph Lo
1
-0
/
+26
2013-07-03
Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux
Linus Torvalds
1
-7
/
+263
2013-06-18
clk: tegra: T114: add DFLL DVCO reset control
Paul Walmsley
1
-0
/
+37
2013-06-18
clk: tegra: T114: add DFLL source clocks
Paul Walmsley
1
-0
/
+11
2013-06-18
clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
Paul Walmsley
1
-0
/
+118
2013-06-12
clk: tegra: override bits for Tegra114 PLLM
Peter De Schrijver
1
-0
/
+9
2013-06-12
clk: tegra: fix sclk_parents
Peter De Schrijver
1
-1
/
+1
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