starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-07-26	clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks	Peter De-Schrijver	1	-11/+0
2018-03-12	clk: tegra: Mark HCLK, SCLK and EMC as critical	Dmitry Osipenko	1	-1/+1
2017-11-01	clk: tegra: Correct parent of the APBDMA clock	Dmitry Osipenko	1	-1/+1
2017-11-01	clk: tegra: Add AHB DMA clock entry	Dmitry Osipenko	1	-0/+1
2017-10-19	clk: tegra: Fix sor1_out clock implementation	Thierry Reding	1	-16/+0
2017-10-19	clk: tegra: Use tegra_clk_register_periph_data()	Thierry Reding	1	-4/+1
2017-08-24	clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C	Alex Frid	1	-1/+2
2017-04-04	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver	1	-0/+6
2017-03-20	clk: tegra: Define Tegra210 DMIC clocks	Peter De Schrijver	1	-0/+21
2017-03-20	clk: tegra: Add CEC clock	Peter De Schrijver	1	-0/+1
2017-03-20	clk: tegra: Correct afi clock parent	Peter De Schrijver	1	-1/+1
2017-03-20	clk: tegra: Fix ISP clock modelling	Peter De Schrijver	1	-2/+9
2016-06-22	clk: tegra: Mark timer clock as critical	Thierry Reding	1	-1/+1
2016-06-17	clk: tegra: Squash sor1 safe/brick/src into a single mux	Thierry Reding	1	-11/+12
2016-04-28	clk: tegra: dpaux and dpaux1 are fixed factor clocks	Thierry Reding	1	-2/+0
2016-04-28	clk: tegra: Add dpaux1 clock	Thierry Reding	1	-0/+1
2016-04-28	clk: tegra: Use correct parent for dpaux clock	Thierry Reding	1	-1/+1
2016-04-28	clk: tegra: Special-case mipi-cal parent on Tegra114	Thierry Reding	1	-1/+1
2016-04-28	clk: tegra: Constify peripheral clock registers	Thierry Reding	1	-1/+1
2016-02-02	clk: tegra: Add the APB2APE audio clock on Tegra210	Jon Hunter	1	-0/+1
2016-02-02	clk: tegra: Fix the misnaming of nvenc from msenc	Rhyland Klein	1	-1/+1
2016-01-25	clk: tegra: Fix divider on VI_I2C	Rhyland Klein	1	-1/+1
2015-11-20	clk: tegra: periph: Add new periph clks and muxes for Tegra210	Rhyland Klein	1	-4/+367
2015-07-20	clk: tegra: Properly include clk.h	Stephen Boyd	1	-1/+0
2015-04-10	clk: tegra: Fix a bunch of sparse warnings	Thierry Reding	1	-1/+1
2015-02-02	clk: tegra: Define PLLD_DSI and remove dsia(b)_mux	Mark Zhang	1	-2/+0
2015-02-02	clk: tegra: SDMMC controllers are on APB	Andrew Bresticker	1	-8/+8
2014-06-25	clk: tegra: fix vi_sensor clocks on Tegra124	Peter De Schrijver	1	-2/+2
2014-05-23	clk: tegra: Fix xusb_hs_src clock hierarchy	Andrew Bresticker	1	-0/+6
2014-05-23	clk: tegra: Fix xusb_fs_src mux	Jim Lin	1	-1/+3
2014-02-20	clk: tegra: Fix vic03 mux index	Peter De Schrijver	1	-3/+1
2014-02-17	clk: tegra: fix sdmmc clks on Tegra1x4	Andrew Bresticker	1	-0/+4
2014-02-17	clk: tegra: Correct clock number for UARTE	Thierry Reding	1	-1/+1
2013-11-26	clk: tegra124: Add new peripheral clocks	Peter De Schrijver	1	-0/+69
2013-11-26	clk: tegra: add TEGRA_PERIPH_NO_GATE	Peter De Schrijver	1	-0/+6
2013-11-26	clk: tegra: add locking to periph clks	Peter De Schrijver	1	-15/+18
2013-11-26	clk: tegra: move periph clocks to common file	Peter De Schrijver	1	-0/+596