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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
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buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
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openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
tegra
/
clk-pll.c
Age
Commit message (
Expand
)
Author
Files
Lines
2014-05-28
Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijv...
Mike Turquette
1
-21
/
+43
2014-05-23
clk: tegra: Enable hardware control of PLLE
Jim Lin
1
-1
/
+32
2014-05-17
clk: tegra: Fix wrong value written to PLLE_AUX
Tuomas Tynkkynen
1
-1
/
+1
2014-04-17
clk: tegra: Fix enabling of PLLE
Thierry Reding
1
-1
/
+1
2014-04-17
clk: tegra: Introduce divider mask and shift helpers
Thierry Reding
1
-20
/
+24
2014-04-17
clk: tegra: Fix PLLE programming
Thierry Reding
1
-6
/
+24
2013-12-20
clk: tegra: Staticize local variables in clk-pll.c
Sachin Kamat
1
-6
/
+6
2013-11-28
clk: tegra: fix __clk_lookup() return value checks
Wei Yongjun
1
-4
/
+4
2013-11-28
clk: tegra: Do not print errors for clk_round_rate()
Thierry Reding
1
-6
/
+3
2013-11-26
clk: tegra: Add support for PLLSS
Peter De Schrijver
1
-2
/
+121
2013-11-26
clk: tegra: move fields to tegra_clk_pll_params
Peter De Schrijver
1
-79
/
+59
2013-11-26
clk: tegra: use pll_ref as the pll_e parent
Peter De Schrijver
1
-3
/
+5
2013-11-26
clk: tegra: move some PLLC and PLLXC init to clk-pll.c
Peter De Schrijver
1
-4
/
+91
2013-11-26
clk: tegra: Fix clock rate computation
Thierry Reding
1
-0
/
+2
2013-11-26
clk: tegra: PLLE spread spectrum control
Peter De Schrijver
1
-1
/
+29
2013-06-12
clk: tegra: Use override bits when needed
Peter De Schrijver
1
-33
/
+49
2013-06-12
clk: tegra: fix pllre initilization
Peter De Schrijver
1
-2
/
+1
2013-06-12
clk: tegra: allow PLL m,n,p init from SoC files
Peter De Schrijver
1
-27
/
+33
2013-06-12
clk: tegra: pllc and pllxc should use pdiv_map
Peter De Schrijver
1
-80
/
+82
2013-04-05
clk: tegra: Add new fields and PLL types for Tegra114
Peter De Schrijver
1
-0
/
+839
2013-04-05
clk: tegra: move from a lock bit idx to a lock mask
Peter De Schrijver
1
-3
/
+3
2013-04-05
clk: tegra: Add PLL post divider table
Peter De Schrijver
1
-6
/
+32
2013-04-05
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
Peter De Schrijver
1
-0
/
+5
2013-04-05
clk: tegra: Add TEGRA_PLL_BYPASS flag
Peter De Schrijver
1
-4
/
+8
2013-04-05
clk: tegra: Refactor PLL programming code
Peter De Schrijver
1
-101
/
+161
2013-01-28
clk: tegra: add Tegra specific clocks
Prashant Gaikwad
1
-0
/
+648
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