index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
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path:
root
/
drivers
/
clk
/
tegra
/
clk-id.h
Age
Commit message (
Expand
)
Author
Files
Lines
2020-03-12
clk: tegra: Remove tegra_pmc_clk_init along with clk ids
Sowjanya Komatineni
1
-7
/
+0
2020-03-12
clk: tegra: Remove CLK_M_DIV fixed clocks
Sowjanya Komatineni
1
-2
/
+0
2020-03-12
clk: tegra: Add Tegra OSC to clock lookup
Sowjanya Komatineni
1
-0
/
+1
2020-03-12
clk: tegra: Add support for OSC_DIV fixed clocks
Sowjanya Komatineni
1
-0
/
+2
2019-11-11
clk: tegra: Rename sor0_lvds to sor0_out
Thierry Reding
1
-1
/
+1
2019-11-11
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
Thierry Reding
1
-1
/
+1
2018-07-26
clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
Peter De-Schrijver
1
-2
/
+0
2017-11-18
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-0
/
+1
2017-11-02
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Greg Kroah-Hartman
1
-0
/
+1
2017-11-01
clk: tegra: Add AHB DMA clock entry
Dmitry Osipenko
1
-0
/
+1
2017-04-04
clk: tegra: Add missing Tegra210 clocks
Peter De Schrijver
1
-0
/
+6
2017-03-20
clk: tegra: Define Tegra210 DMIC clocks
Peter De Schrijver
1
-1
/
+4
2017-03-20
clk: tegra: Define Tegra210 DMIC sync clocks
Peter De Schrijver
1
-0
/
+6
2017-03-20
clk: tegra: Add CEC clock
Peter De Schrijver
1
-0
/
+1
2017-03-20
clk: tegra: Fix ISP clock modelling
Peter De Schrijver
1
-0
/
+1
2016-06-17
clk: tegra: Squash sor1 safe/brick/src into a single mux
Thierry Reding
1
-1
/
+0
2016-04-28
clk: tegra: Add sor_safe clock
Thierry Reding
1
-0
/
+1
2016-04-28
clk: tegra: Add dpaux1 clock
Thierry Reding
1
-0
/
+1
2016-02-02
clk: tegra: Add the APB2APE audio clock on Tegra210
Jon Hunter
1
-0
/
+1
2015-12-17
clk: tegra: Add support for Tegra210 clocks
Rhyland Klein
1
-0
/
+7
2015-11-20
clk: tegra: periph: Add new periph clks and muxes for Tegra210
Rhyland Klein
1
-1
/
+67
2015-02-02
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
Mark Zhang
1
-2
/
+0
2014-05-23
clk: tegra: Fix xusb_hs_src clock hierarchy
Andrew Bresticker
1
-0
/
+1
2014-02-17
clk: tegra: fix sdmmc clks on Tegra1x4
Andrew Bresticker
1
-0
/
+4
2013-11-26
clk: tegra124: Add common clk IDs to clk-id.h
Peter De Schrijver
1
-0
/
+22
2013-11-26
clk: tegra: add header for common tegra clock IDs
Peter De Schrijver
1
-0
/
+213