| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-11-11 | clk: tegra: clk-dfll: Add suspend and resume support | Sowjanya Komatineni | 1 | -0/+2 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner | 1 | -9/+1 |
| 2019-02-06 | clk: tegra: dfll: CVB calculation alignment with the regulator | Joseph Lo | 1 | -1/+5 |
| 2017-11-01 | clk: tegra: dfll: Fix drvdata overwriting issue | Nicolin Chen | 1 | -1/+1 |
| 2016-04-28 | clk: tegra: dfll: Properly clean up on failure and removal | Thierry Reding | 1 | -0/+2 |
| 2016-04-28 | clk: tegra: dfll: Reference CVB table instead of copying data | Thierry Reding | 1 | -8/+2 |
| 2016-04-28 | clk: tegra: dfll: Update kerneldoc | Thierry Reding | 1 | -5/+5 |
| 2015-07-16 | clk: tegra: Add Tegra124 DFLL clocksource platform driver | Tuomas Tynkkynen | 1 | -1/+1 |
| 2015-07-16 | clk: tegra: Add library for the DFLL clock source (open-loop mode) | Tuomas Tynkkynen | 1 | -0/+54 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |